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llvm-6502/lib/Target/XCore/Makefile

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Test commit, add Makefile for XCore target, more to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 09:53:58 +00:00
##===- lib/Target/XCore/Makefile ---------------------------*- Makefile -*-===##
Removed trailing whitespace from Makefiles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61991 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-09 16:44:42 +00:00
#
Test commit, add Makefile for XCore target, more to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 09:53:58 +00:00
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
Stop building RTTI information for *most* llvm libraries. Notable missing ones are libsupport, libsystem and libvmcore. libvmcore is currently blocked on bugpoint, which uses EH. Once it stops using EH, we can switch it off. This #if 0's out 3 unit tests, because gtest requires RTTI information. Suggestions welcome on how to fix this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 06:49:46 +00:00
Test commit, add Makefile for XCore target, more to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 09:53:58 +00:00
LEVEL = ../../..
Move XCore AsmPrinter to XCore/AsmPrinter directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79094 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 12:53:15 +00:00
LIBRARYNAME = LLVMXCoreCodeGen
Test commit, add Makefile for XCore target, more to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 09:53:58 +00:00
TARGET = XCore
# Make sure that tblgen is run, first thing.
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 20:07:07 +00:00
BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \
XCoreGenAsmWriter.inc \
Test commit, add Makefile for XCore target, more to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 09:53:58 +00:00
XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 22:36:09 +00:00
XCoreGenSubtargetInfo.inc
Test commit, add Makefile for XCore target, more to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 09:53:58 +00:00
Next round of MC refactoring. This patch factor MC table instantiations, MC registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 20:59:42 +00:00
DIRS = TargetInfo MCTargetDesc
Add TargetInfo libraries for all targets. - Intended to match current TargetMachine implementations. - No facilities for linking these in yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 06:35:19 +00:00
Test commit, add Makefile for XCore target, more to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 09:53:58 +00:00
include $(LEVEL)/Makefile.common
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