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llvm-6502/test/CodeGen/PowerPC/lsa.ll

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Update the cpu specified on some PPC regression tests Some of these tests did not specify a cpu but were also sensitive to instruction scheduling and/or register assignment choices. A few others similarly-sensitive tests specified a cpu (often the POWER7), and while the P7 currently uses the default model for PPC64, this will soon change. For those tests which should not really be cpu-dependent anyway, the cpu is set to the generic 'ppc64'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195977 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-30 19:39:27 +00:00
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=ppc64 | FileCheck %s
Use virtual base registers on PPC On PowerPC, non-vector loads and stores have r+i forms; however, in functions with large stack frames these were not being used to access slots far from the stack pointer because such slots were out of range for the signed 16-bit immediate offset field. This increases register pressure because we need a separate register for each offset (when the r+r form is used). By enabling virtual base registers, we can deal with large stack frames without unduly increasing register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 17:27:09 +00:00
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define signext i32 @foo() #0 {
entry:
%v = alloca [8200 x i32], align 4
%w = alloca [8200 x i32], align 4
%q = alloca [8200 x i32], align 4
%0 = bitcast [8200 x i32]* %v to i8*
call void @llvm.lifetime.start(i64 32800, i8* %0) #0
%1 = bitcast [8200 x i32]* %w to i8*
call void @llvm.lifetime.start(i64 32800, i8* %1) #0
%2 = bitcast [8200 x i32]* %q to i8*
call void @llvm.lifetime.start(i64 32800, i8* %2) #0
%arraydecay = getelementptr inbounds [8200 x i32]* %q, i64 0, i64 0
%arraydecay1 = getelementptr inbounds [8200 x i32]* %v, i64 0, i64 0
%arraydecay2 = getelementptr inbounds [8200 x i32]* %w, i64 0, i64 0
call void @bar(i32* %arraydecay, i32* %arraydecay1, i32* %arraydecay2) #0
TBAA: remove !tbaa from testing cases if not used. This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 17:52:57 +00:00
%3 = load i32* %arraydecay2, align 4
Use virtual base registers on PPC On PowerPC, non-vector loads and stores have r+i forms; however, in functions with large stack frames these were not being used to access slots far from the stack pointer because such slots were out of range for the signed 16-bit immediate offset field. This increases register pressure because we need a separate register for each offset (when the r+r form is used). By enabling virtual base registers, we can deal with large stack frames without unduly increasing register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 17:27:09 +00:00
%arrayidx3 = getelementptr inbounds [8200 x i32]* %w, i64 0, i64 1
TBAA: remove !tbaa from testing cases if not used. This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 17:52:57 +00:00
%4 = load i32* %arrayidx3, align 4
Use virtual base registers on PPC On PowerPC, non-vector loads and stores have r+i forms; however, in functions with large stack frames these were not being used to access slots far from the stack pointer because such slots were out of range for the signed 16-bit immediate offset field. This increases register pressure because we need a separate register for each offset (when the r+r form is used). By enabling virtual base registers, we can deal with large stack frames without unduly increasing register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 17:27:09 +00:00
; CHECK: @foo
; CHECK-NOT: lwzx
; CHECK: lwz {{[0-9]+}}, 4([[REG:[0-9]+]])
; CHECK: lwz {{[0-9]+}}, 0([[REG]])
; CHECK: blr
%add = add nsw i32 %4, %3
call void @llvm.lifetime.end(i64 32800, i8* %2) #0
call void @llvm.lifetime.end(i64 32800, i8* %1) #0
call void @llvm.lifetime.end(i64 32800, i8* %0) #0
ret i32 %add
}
declare void @llvm.lifetime.start(i64, i8* nocapture) #0
declare void @bar(i32*, i32*, i32*)
declare void @llvm.lifetime.end(i64, i8* nocapture) #0
attributes #0 = { nounwind }
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