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llvm-6502/test/CodeGen/X86/2007-01-08-InstrSched.ll

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Add PR number for future reference git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33031 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-09 00:31:52 +00:00
; PR1075
Don't enable the post-RA scheduler on x86 except at -O3. In its current form, it is too expensive in compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-07 19:04:31 +00:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -O3 | FileCheck %s
Added a test case from PR1075. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33028 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-08 23:58:27 +00:00
eliminate some uses of prcontext. Any help here would be appreciated :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80520 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-30 21:45:23 +00:00
define float @foo(float %x) nounwind {
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
%tmp1 = fmul float %x, 3.000000e+00
%tmp3 = fmul float %x, 5.000000e+00
%tmp5 = fmul float %x, 7.000000e+00
%tmp7 = fmul float %x, 1.100000e+01
%tmp10 = fadd float %tmp1, %tmp3
%tmp12 = fadd float %tmp10, %tmp5
%tmp14 = fadd float %tmp12, %tmp7
Added a test case from PR1075. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33028 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-08 23:58:27 +00:00
ret float %tmp14
eliminate some uses of prcontext. Any help here would be appreciated :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80520 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-30 21:45:23 +00:00
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 22:17:20 +00:00
; CHECK: mulss
; CHECK: mulss
Turning off post-ra scheduling for x86. It isn't a consistent win. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 06:55:42 +00:00
; CHECK: addss
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 22:17:20 +00:00
; CHECK: mulss
Turning off post-ra scheduling for x86. It isn't a consistent win. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 06:55:42 +00:00
; CHECK: addss
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 22:17:20 +00:00
; CHECK: mulss
Turning off post-ra scheduling for x86. It isn't a consistent win. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 06:55:42 +00:00
; CHECK: addss
; CHECK: ret
Added a test case from PR1075. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33028 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-08 23:58:27 +00:00
}
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