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llvm-6502/test/CodeGen/X86/constant-pool-remat-0.ll

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--- Merging r127731 into '.': U test/CodeGen/X86/byval2.ll U test/CodeGen/X86/byval4.ll U test/CodeGen/X86/byval.ll U test/CodeGen/X86/byval3.ll U test/CodeGen/X86/byval5.ll --- Merging r127732 into '.': U test/CodeGen/X86/stdarg.ll U test/CodeGen/X86/fold-mul-lohi.ll U test/CodeGen/X86/scalar-min-max-fill-operand.ll U test/CodeGen/X86/tailcallbyval64.ll U test/CodeGen/X86/stride-reuse.ll U test/CodeGen/X86/sse-align-3.ll U test/CodeGen/X86/sse-commute.ll U test/CodeGen/X86/stride-nine-with-base-reg.ll U test/CodeGen/X86/coalescer-commute2.ll U test/CodeGen/X86/sse-align-7.ll U test/CodeGen/X86/sse_reload_fold.ll U test/CodeGen/X86/sse-align-0.ll --- Merging r127733 into '.': U test/CodeGen/X86/peep-vector-extract-concat.ll U test/CodeGen/X86/pmulld.ll U test/CodeGen/X86/widen_load-0.ll U test/CodeGen/X86/v2f32.ll U test/CodeGen/X86/apm.ll U test/CodeGen/X86/h-register-store.ll U test/CodeGen/X86/h-registers-0.ll --- Merging r127734 into '.': U test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll U test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll U test/CodeGen/X86/avoid-lea-scale2.ll U test/CodeGen/X86/lea-3.ll U test/CodeGen/X86/vec_set-8.ll U test/CodeGen/X86/i64-mem-copy.ll U test/CodeGen/X86/x86-64-malloc.ll U test/CodeGen/X86/mmx-copy-gprs.ll U test/CodeGen/X86/vec_shuffle-17.ll U test/CodeGen/X86/2007-07-18-Vector-Extract.ll --- Merging r127775 into '.': U test/CodeGen/X86/constant-pool-remat-0.ll --- Merging r127872 into '.': U utils/lit/lit/TestingConfig.py U lib/Support/raw_ostream.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 06:22:54 +00:00
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
; CHECK: LCPI
; CHECK: LCPI
; CHECK: LCPI
; CHECK-NOT: LCPI
; RUN: llc < %s -mtriple=x86_64-linux -o /dev/null -stats -info-output-file - | FileCheck %s -check-prefix=X64stat
; X64stat: 6 asm-printer
; RUN: llc < %s -march=x86 -mattr=+sse2 -o /dev/null -stats -info-output-file - | FileCheck %s -check-prefix=X32stat
; X32stat: 12 asm-printer
Mark the SSE and MMX load instructions that X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle with the isReMaterializable flag so that it is given a chance to handle them. Without hoisting constant-pool loads from loops this isn't very visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from making a copy of the constant pool on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 14:27:55 +00:00
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 17:24:07 +00:00
declare float @qux(float %y)
Mark the SSE and MMX load instructions that X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle with the isReMaterializable flag so that it is given a chance to handle them. Without hoisting constant-pool loads from loops this isn't very visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from making a copy of the constant pool on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 14:27:55 +00:00
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 17:24:07 +00:00
define float @array(float %a) nounwind {
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
%n = fmul float %a, 9.0
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05 17:24:07 +00:00
%m = call float @qux(float %n)
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
%o = fmul float %m, 9.0
Mark the SSE and MMX load instructions that X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle with the isReMaterializable flag so that it is given a chance to handle them. Without hoisting constant-pool loads from loops this isn't very visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from making a copy of the constant pool on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 14:27:55 +00:00
ret float %o
}
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