llvm-6502/lib/Target/CellSPU/SPUTargetMachine.h

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//===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU ----*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the CellSPU-specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
#ifndef SPU_TARGETMACHINE_H
#define SPU_TARGETMACHINE_H
#include "SPUSubtarget.h"
#include "SPUInstrInfo.h"
#include "SPUISelLowering.h"
#include "SPUFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
namespace llvm {
class PassManager;
class GlobalValue;
class TargetFrameInfo;
/// SPUTargetMachine
///
class SPUTargetMachine : public LLVMTargetMachine {
SPUSubtarget Subtarget;
const TargetData DataLayout;
SPUInstrInfo InstrInfo;
SPUFrameInfo FrameInfo;
SPUTargetLowering TLInfo;
InstrItineraryData InstrItins;
protected:
virtual const TargetAsmInfo *createTargetAsmInfo() const;
public:
Reapply TargetRegistry refactoring commits. --- Reverse-merging r75799 into '.': U test/Analysis/PointerTracking U include/llvm/Target/TargetMachineRegistry.h U include/llvm/Target/TargetMachine.h U include/llvm/Target/TargetRegistry.h U include/llvm/Target/TargetSelect.h U tools/lto/LTOCodeGenerator.cpp U tools/lto/LTOModule.cpp U tools/llc/llc.cpp U lib/Target/PowerPC/PPCTargetMachine.h U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp U lib/Target/PowerPC/PPCTargetMachine.cpp U lib/Target/PowerPC/PPC.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/ARMTargetMachine.h U lib/Target/ARM/ARM.h U lib/Target/XCore/XCoreTargetMachine.cpp U lib/Target/XCore/XCoreTargetMachine.h U lib/Target/PIC16/PIC16TargetMachine.cpp U lib/Target/PIC16/PIC16TargetMachine.h U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp U lib/Target/Alpha/AlphaTargetMachine.cpp U lib/Target/Alpha/AlphaTargetMachine.h U lib/Target/X86/X86TargetMachine.h U lib/Target/X86/X86.h U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86TargetMachine.cpp U lib/Target/MSP430/MSP430TargetMachine.cpp U lib/Target/MSP430/MSP430TargetMachine.h U lib/Target/CppBackend/CPPTargetMachine.h U lib/Target/CppBackend/CPPBackend.cpp U lib/Target/CBackend/CTargetMachine.h U lib/Target/CBackend/CBackend.cpp U lib/Target/TargetMachine.cpp U lib/Target/IA64/IA64TargetMachine.cpp U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp U lib/Target/IA64/IA64TargetMachine.h U lib/Target/IA64/IA64.h U lib/Target/MSIL/MSILWriter.cpp U lib/Target/CellSPU/SPUTargetMachine.h U lib/Target/CellSPU/SPU.h U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp U lib/Target/CellSPU/SPUTargetMachine.cpp U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp U lib/Target/Mips/MipsTargetMachine.cpp U lib/Target/Mips/MipsTargetMachine.h U lib/Target/Mips/Mips.h U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp U lib/Target/Sparc/SparcTargetMachine.cpp U lib/Target/Sparc/SparcTargetMachine.h U lib/ExecutionEngine/JIT/TargetSelect.cpp U lib/Support/TargetRegistry.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 20:24:03 +00:00
SPUTargetMachine(const Target &T, const Module &M, const std::string &FS);
/// Return the subtarget implementation object
virtual const SPUSubtarget *getSubtargetImpl() const {
return &Subtarget;
}
virtual const SPUInstrInfo *getInstrInfo() const {
return &InstrInfo;
}
virtual const SPUFrameInfo *getFrameInfo() const {
return &FrameInfo;
}
/*!
\note Cell SPU does not support JIT today. It could support JIT at some
point.
*/
virtual TargetJITInfo *getJITInfo() {
return NULL;
}
virtual SPUTargetLowering *getTargetLowering() const {
return const_cast<SPUTargetLowering*>(&TLInfo);
}
virtual const SPURegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual const TargetData *getTargetData() const {
return &DataLayout;
}
virtual const InstrItineraryData getInstrItineraryData() const {
return InstrItins;
}
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel);
};
} // end namespace llvm
#endif