2008-08-13 20:19:35 +00:00
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///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the FastISel class.
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//
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2008-09-30 20:48:29 +00:00
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// "Fast" instruction selection is designed to emit very poor code quickly.
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// Also, it is not designed to be able to do much lowering, so most illegal
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2008-10-13 01:59:13 +00:00
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// types (e.g. i64 on 32-bit targets) and operations are not supported. It is
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// also not intended to be able to do much optimization, except in a few cases
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// where doing optimizations reduces overall compile time. For example, folding
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// constants into immediate fields is often done, because it's cheap and it
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// reduces the number of instructions later phases have to examine.
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2008-09-30 20:48:29 +00:00
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//
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// "Fast" instruction selection is able to fail gracefully and transfer
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// control to the SelectionDAG selector for operations that it doesn't
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2008-10-13 01:59:13 +00:00
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// support. In many cases, this allows us to avoid duplicating a lot of
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2008-09-30 20:48:29 +00:00
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// the complicated lowering logic that SelectionDAG currently has.
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//
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// The intended use for "fast" instruction selection is "-O0" mode
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// compilation, where the quality of the generated code is irrelevant when
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2008-10-13 01:59:13 +00:00
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// weighed against the speed at which the code can be generated. Also,
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2008-09-30 20:48:29 +00:00
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// at -O0, the LLVM optimizers are not running, and this makes the
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// compile time of codegen a much higher portion of the overall compile
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2008-10-13 01:59:13 +00:00
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// time. Despite its limitations, "fast" instruction selection is able to
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2008-09-30 20:48:29 +00:00
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// handle enough code on its own to provide noticeable overall speedups
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// in -O0 compiles.
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//
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// Basic operations are supported in a target-independent way, by reading
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// the same instruction descriptions that the SelectionDAG selector reads,
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// and identifying simple arithmetic operations that can be directly selected
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2008-10-13 01:59:13 +00:00
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// from simple operators. More complicated operations currently require
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2008-09-30 20:48:29 +00:00
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// target-specific code.
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//
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2008-08-13 20:19:35 +00:00
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//===----------------------------------------------------------------------===//
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2008-09-25 17:05:24 +00:00
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#include "llvm/Function.h"
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#include "llvm/GlobalVariable.h"
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2008-08-19 22:31:46 +00:00
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#include "llvm/Instructions.h"
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2008-09-25 17:05:24 +00:00
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#include "llvm/IntrinsicInst.h"
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2008-08-13 20:19:35 +00:00
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2008-09-25 17:05:24 +00:00
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2008-08-13 20:19:35 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-08-20 22:45:34 +00:00
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#include "llvm/Target/TargetData.h"
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2008-08-13 20:19:35 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2008-08-20 22:45:34 +00:00
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#include "llvm/Target/TargetLowering.h"
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2008-08-20 21:05:57 +00:00
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#include "llvm/Target/TargetMachine.h"
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2008-08-13 20:19:35 +00:00
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using namespace llvm;
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2008-09-03 23:12:08 +00:00
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unsigned FastISel::getRegForValue(Value *V) {
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2008-09-03 23:32:19 +00:00
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// Look up the value to see if we already have a register for it. We
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// cache values defined by Instructions across blocks, and other values
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// only locally. This is because Instructions already have the SSA
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// def-dominatess-use requirement enforced.
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2008-09-03 17:37:03 +00:00
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if (ValueMap.count(V))
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return ValueMap[V];
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2008-09-03 23:32:19 +00:00
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unsigned Reg = LocalValueMap[V];
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if (Reg != 0)
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return Reg;
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2008-08-27 18:10:19 +00:00
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MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
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2008-09-10 21:01:08 +00:00
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// Ignore illegal types.
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if (!TLI.isTypeLegal(VT)) {
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// Promote MVT::i1 to a legal type though, because it's common and easy.
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if (VT == MVT::i1)
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VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
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else
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return 0;
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}
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2008-08-27 18:10:19 +00:00
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if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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2008-09-19 22:16:54 +00:00
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if (CI->getValue().getActiveBits() <= 64)
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Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
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2008-09-10 20:11:02 +00:00
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} else if (isa<AllocaInst>(V)) {
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2008-09-19 22:16:54 +00:00
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Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
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2008-08-28 21:19:07 +00:00
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} else if (isa<ConstantPointerNull>(V)) {
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2008-10-07 22:03:27 +00:00
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// Translate this as an integer zero so that it can be
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// local-CSE'd with actual integer zeros.
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Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
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2008-08-27 18:10:19 +00:00
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} else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
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2008-09-03 23:32:19 +00:00
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Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
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2008-08-27 18:10:19 +00:00
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if (!Reg) {
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const APFloat &Flt = CF->getValueAPF();
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MVT IntVT = TLI.getPointerTy();
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uint64_t x[2];
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uint32_t IntBitWidth = IntVT.getSizeInBits();
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2008-10-09 23:00:39 +00:00
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bool isExact;
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(void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
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APFloat::rmTowardZero, &isExact);
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if (isExact) {
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2008-09-19 22:16:54 +00:00
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APInt IntVal(IntBitWidth, 2, x);
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2008-08-27 18:10:19 +00:00
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2008-10-07 22:03:27 +00:00
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unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
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2008-09-19 22:16:54 +00:00
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if (IntegerReg != 0)
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Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
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}
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2008-08-27 18:10:19 +00:00
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}
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2008-09-05 18:18:20 +00:00
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} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
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if (!SelectOperator(CE, CE->getOpcode())) return 0;
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Reg = LocalValueMap[CE];
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2008-08-28 21:19:07 +00:00
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} else if (isa<UndefValue>(V)) {
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2008-09-03 23:32:19 +00:00
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Reg = createResultReg(TLI.getRegClassFor(VT));
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2008-08-28 21:19:07 +00:00
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BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
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2008-08-27 18:10:19 +00:00
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}
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2008-09-03 17:51:57 +00:00
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2008-09-25 01:28:51 +00:00
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// If target-independent code couldn't handle the value, give target-specific
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// code a try.
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2008-09-05 23:36:01 +00:00
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if (!Reg && isa<Constant>(V))
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2008-09-19 22:16:54 +00:00
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Reg = TargetMaterializeConstant(cast<Constant>(V));
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2008-09-05 23:36:01 +00:00
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2008-09-19 22:16:54 +00:00
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// Don't cache constant materializations in the general ValueMap.
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// To do so would require tracking what uses they dominate.
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2008-09-25 01:28:51 +00:00
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if (Reg != 0)
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LocalValueMap[V] = Reg;
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2008-09-03 23:32:19 +00:00
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return Reg;
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2008-08-27 18:10:19 +00:00
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}
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2008-09-09 01:26:59 +00:00
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unsigned FastISel::lookUpRegForValue(Value *V) {
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// Look up the value to see if we already have a register for it. We
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// cache values defined by Instructions across blocks, and other values
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// only locally. This is because Instructions already have the SSA
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// def-dominatess-use requirement enforced.
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if (ValueMap.count(V))
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return ValueMap[V];
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return LocalValueMap[V];
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}
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2008-08-30 00:38:46 +00:00
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/// UpdateValueMap - Update the value map to include the new mapping for this
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/// instruction, or insert an extra copy to get the result in a previous
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/// determined register.
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/// NOTE: This is only necessary because we might select a block that uses
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/// a value before we select the block that defines the value. It might be
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/// possible to fix this by selecting blocks in reverse postorder.
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2008-09-05 00:06:23 +00:00
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void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
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2008-09-05 18:18:20 +00:00
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if (!isa<Instruction>(I)) {
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LocalValueMap[I] = Reg;
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return;
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}
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2008-08-30 00:38:46 +00:00
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if (!ValueMap.count(I))
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ValueMap[I] = Reg;
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else
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2008-09-07 09:04:52 +00:00
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TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
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Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
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2008-08-30 00:38:46 +00:00
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}
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2008-08-20 00:11:48 +00:00
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// which has an opcode which directly corresponds to the given ISD opcode.
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///
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2008-09-05 18:18:20 +00:00
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bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
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2008-08-21 01:41:07 +00:00
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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2008-09-05 18:44:22 +00:00
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2008-08-26 20:52:40 +00:00
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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2008-09-05 18:44:22 +00:00
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if (!TLI.isTypeLegal(VT)) {
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2008-09-25 17:22:52 +00:00
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// MVT::i1 is special. Allow AND, OR, or XOR because they
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2008-09-05 18:44:22 +00:00
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// don't require additional zeroing, which makes them easy.
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if (VT == MVT::i1 &&
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2008-09-25 17:22:52 +00:00
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(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
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ISDOpcode == ISD::XOR))
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2008-09-05 18:44:22 +00:00
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VT = TLI.getTypeToTransformTo(VT);
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else
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return false;
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}
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2008-08-21 01:41:07 +00:00
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2008-09-03 23:12:08 +00:00
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unsigned Op0 = getRegForValue(I->getOperand(0));
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2008-08-21 01:41:07 +00:00
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if (Op0 == 0)
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2008-08-20 00:35:17 +00:00
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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2008-08-21 01:41:07 +00:00
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// Check if the second operand is a constant and handle it appropriately.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
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2008-08-27 18:10:19 +00:00
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unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, CI->getZExtValue());
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if (ResultReg != 0) {
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// We successfully emitted code for the given LLVM Instruction.
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2008-09-03 23:12:08 +00:00
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UpdateValueMap(I, ResultReg);
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2008-08-27 18:10:19 +00:00
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return true;
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}
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2008-08-21 01:41:07 +00:00
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}
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2008-08-27 01:09:54 +00:00
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// Check if the second operand is a constant float.
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if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
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2008-08-27 18:10:19 +00:00
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unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, CF);
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if (ResultReg != 0) {
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// We successfully emitted code for the given LLVM Instruction.
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2008-09-03 23:12:08 +00:00
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UpdateValueMap(I, ResultReg);
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2008-08-27 18:10:19 +00:00
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return true;
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}
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2008-08-27 01:09:54 +00:00
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}
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2008-09-03 23:12:08 +00:00
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unsigned Op1 = getRegForValue(I->getOperand(1));
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2008-08-21 01:41:07 +00:00
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if (Op1 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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2008-08-20 00:11:48 +00:00
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return false;
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2008-08-27 18:10:19 +00:00
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// Now we have both operands in registers. Emit the instruction.
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2008-08-25 23:58:18 +00:00
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unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
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ISDOpcode, Op0, Op1);
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2008-08-20 00:11:48 +00:00
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if (ResultReg == 0)
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// Target-specific code wasn't able to find a machine opcode for
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// the given ISD opcode and type. Halt "fast" selection and bail.
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return false;
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2008-08-20 00:23:20 +00:00
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// We successfully emitted code for the given LLVM Instruction.
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2008-09-03 23:12:08 +00:00
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UpdateValueMap(I, ResultReg);
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2008-08-20 00:11:48 +00:00
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return true;
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}
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2008-09-05 18:18:20 +00:00
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bool FastISel::SelectGetElementPtr(User *I) {
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2008-09-03 23:12:08 +00:00
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unsigned N = getRegForValue(I->getOperand(0));
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2008-08-20 22:45:34 +00:00
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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const Type *Ty = I->getOperand(0)->getType();
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2008-08-21 17:25:26 +00:00
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MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
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2008-08-20 22:45:34 +00:00
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for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
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OI != E; ++OI) {
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Value *Idx = *OI;
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if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
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unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
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if (Field) {
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// N = N + Offset
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uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
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// FIXME: This can be optimized by combining the add with a
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// subsequent one.
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2008-08-21 17:25:26 +00:00
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N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
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2008-08-20 22:45:34 +00:00
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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Ty = StTy->getElementType(Field);
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} else {
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Ty = cast<SequentialType>(Ty)->getElementType();
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// If this is a constant subscript, handle it quickly.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
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if (CI->getZExtValue() == 0) continue;
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uint64_t Offs =
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TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
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2008-08-21 17:25:26 +00:00
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N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
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2008-08-20 22:45:34 +00:00
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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continue;
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}
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// N = N + Idx * ElementSize;
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uint64_t ElementSize = TD.getABITypeSize(Ty);
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2008-09-03 23:12:08 +00:00
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unsigned IdxN = getRegForValue(Idx);
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2008-08-20 22:45:34 +00:00
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if (IdxN == 0)
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|
// Unhandled operand. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If the index is smaller or larger than intptr_t, truncate or extend
|
|
|
|
// it.
|
2008-08-21 01:19:11 +00:00
|
|
|
MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
|
2008-08-20 22:45:34 +00:00
|
|
|
if (IdxVT.bitsLT(VT))
|
2008-08-26 20:57:08 +00:00
|
|
|
IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
|
2008-08-20 22:45:34 +00:00
|
|
|
else if (IdxVT.bitsGT(VT))
|
2008-08-26 20:57:08 +00:00
|
|
|
IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
|
2008-08-20 22:45:34 +00:00
|
|
|
if (IdxN == 0)
|
|
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
|
2008-08-26 20:57:08 +00:00
|
|
|
if (ElementSize != 1) {
|
2008-08-21 17:37:05 +00:00
|
|
|
IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
|
2008-08-26 20:57:08 +00:00
|
|
|
if (IdxN == 0)
|
|
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
}
|
2008-08-25 23:58:18 +00:00
|
|
|
N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
|
2008-08-20 22:45:34 +00:00
|
|
|
if (N == 0)
|
|
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// We successfully emitted code for the given LLVM Instruction.
|
2008-09-03 23:12:08 +00:00
|
|
|
UpdateValueMap(I, N);
|
2008-08-20 22:45:34 +00:00
|
|
|
return true;
|
2008-08-20 00:11:48 +00:00
|
|
|
}
|
|
|
|
|
2008-09-25 17:05:24 +00:00
|
|
|
bool FastISel::SelectCall(User *I) {
|
|
|
|
Function *F = cast<CallInst>(I)->getCalledFunction();
|
|
|
|
if (!F) return false;
|
|
|
|
|
|
|
|
unsigned IID = F->getIntrinsicID();
|
|
|
|
switch (IID) {
|
|
|
|
default: break;
|
|
|
|
case Intrinsic::dbg_stoppoint: {
|
|
|
|
DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
|
|
|
|
if (MMI && SPI->getContext() && MMI->Verify(SPI->getContext())) {
|
|
|
|
DebugInfoDesc *DD = MMI->getDescFor(SPI->getContext());
|
|
|
|
assert(DD && "Not a debug information descriptor");
|
|
|
|
const CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
|
|
|
|
unsigned SrcFile = MMI->RecordSource(CompileUnit);
|
|
|
|
unsigned Line = SPI->getLine();
|
|
|
|
unsigned Col = SPI->getColumn();
|
|
|
|
unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
|
|
|
|
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
|
|
|
|
BuildMI(MBB, II).addImm(ID);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
case Intrinsic::dbg_region_start: {
|
|
|
|
DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
|
|
|
|
if (MMI && RSI->getContext() && MMI->Verify(RSI->getContext())) {
|
|
|
|
unsigned ID = MMI->RecordRegionStart(RSI->getContext());
|
|
|
|
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
|
|
|
|
BuildMI(MBB, II).addImm(ID);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
case Intrinsic::dbg_region_end: {
|
|
|
|
DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
|
|
|
|
if (MMI && REI->getContext() && MMI->Verify(REI->getContext())) {
|
|
|
|
unsigned ID = MMI->RecordRegionEnd(REI->getContext());
|
|
|
|
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
|
|
|
|
BuildMI(MBB, II).addImm(ID);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
case Intrinsic::dbg_func_start: {
|
|
|
|
if (!MMI) return true;
|
|
|
|
DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
|
|
|
|
Value *SP = FSI->getSubprogram();
|
|
|
|
if (SP && MMI->Verify(SP)) {
|
|
|
|
// llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
|
|
|
|
// what (most?) gdb expects.
|
|
|
|
DebugInfoDesc *DD = MMI->getDescFor(SP);
|
|
|
|
assert(DD && "Not a debug information descriptor");
|
|
|
|
SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
|
|
|
|
const CompileUnitDesc *CompileUnit = Subprogram->getFile();
|
|
|
|
unsigned SrcFile = MMI->RecordSource(CompileUnit);
|
|
|
|
// Record the source line but does create a label. It will be emitted
|
|
|
|
// at asm emission time.
|
|
|
|
MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
case Intrinsic::dbg_declare: {
|
|
|
|
DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
|
|
|
|
Value *Variable = DI->getVariable();
|
|
|
|
if (MMI && Variable && MMI->Verify(Variable)) {
|
|
|
|
// Determine the address of the declared object.
|
|
|
|
Value *Address = DI->getAddress();
|
|
|
|
if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
|
|
|
|
Address = BCI->getOperand(0);
|
|
|
|
AllocaInst *AI = dyn_cast<AllocaInst>(Address);
|
|
|
|
// Don't handle byval struct arguments, for example.
|
|
|
|
if (!AI) break;
|
|
|
|
DenseMap<const AllocaInst*, int>::iterator SI =
|
|
|
|
StaticAllocaMap.find(AI);
|
|
|
|
assert(SI != StaticAllocaMap.end() && "Invalid dbg.declare!");
|
|
|
|
int FI = SI->second;
|
|
|
|
|
|
|
|
// Determine the debug globalvariable.
|
|
|
|
GlobalValue *GV = cast<GlobalVariable>(Variable);
|
|
|
|
|
|
|
|
// Build the DECLARE instruction.
|
|
|
|
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
|
|
|
|
BuildMI(MBB, II).addFrameIndex(FI).addGlobalAddress(GV);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-09-05 18:18:20 +00:00
|
|
|
bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
|
2008-08-27 18:58:30 +00:00
|
|
|
MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
|
|
|
|
MVT DstVT = TLI.getValueType(I->getType());
|
2008-08-26 23:46:32 +00:00
|
|
|
|
|
|
|
if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
|
|
|
|
DstVT == MVT::Other || !DstVT.isSimple() ||
|
2008-10-03 01:28:47 +00:00
|
|
|
!TLI.isTypeLegal(DstVT))
|
2008-08-26 23:46:32 +00:00
|
|
|
// Unhandled type. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
|
2008-10-03 01:28:47 +00:00
|
|
|
// Check if the source operand is legal. Or as a special case,
|
|
|
|
// it may be i1 if we're doing zero-extension because that's
|
|
|
|
// trivially easy and somewhat common.
|
|
|
|
if (!TLI.isTypeLegal(SrcVT)) {
|
|
|
|
if (SrcVT == MVT::i1 && Opcode == ISD::ZERO_EXTEND)
|
|
|
|
SrcVT = TLI.getTypeToTransformTo(SrcVT);
|
|
|
|
else
|
|
|
|
// Unhandled type. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
unsigned InputReg = getRegForValue(I->getOperand(0));
|
2008-08-26 23:46:32 +00:00
|
|
|
if (!InputReg)
|
|
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
|
|
|
|
DstVT.getSimpleVT(),
|
|
|
|
Opcode,
|
|
|
|
InputReg);
|
|
|
|
if (!ResultReg)
|
|
|
|
return false;
|
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
UpdateValueMap(I, ResultReg);
|
2008-08-26 23:46:32 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-09-05 18:18:20 +00:00
|
|
|
bool FastISel::SelectBitCast(User *I) {
|
2008-08-27 18:10:19 +00:00
|
|
|
// If the bitcast doesn't change the type, just use the operand value.
|
|
|
|
if (I->getType() == I->getOperand(0)->getType()) {
|
2008-09-03 23:12:08 +00:00
|
|
|
unsigned Reg = getRegForValue(I->getOperand(0));
|
2008-08-27 20:41:38 +00:00
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
2008-09-03 23:12:08 +00:00
|
|
|
UpdateValueMap(I, Reg);
|
2008-08-27 18:10:19 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
|
2008-08-27 18:58:30 +00:00
|
|
|
MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
|
|
|
|
MVT DstVT = TLI.getValueType(I->getType());
|
2008-08-26 23:46:32 +00:00
|
|
|
|
|
|
|
if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
|
|
|
|
DstVT == MVT::Other || !DstVT.isSimple() ||
|
|
|
|
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
|
|
|
|
// Unhandled type. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
unsigned Op0 = getRegForValue(I->getOperand(0));
|
2008-08-27 18:10:19 +00:00
|
|
|
if (Op0 == 0)
|
|
|
|
// Unhandled operand. Halt "fast" selection and bail.
|
2008-08-26 23:46:32 +00:00
|
|
|
return false;
|
|
|
|
|
2008-08-27 18:10:19 +00:00
|
|
|
// First, try to perform the bitcast by inserting a reg-reg copy.
|
|
|
|
unsigned ResultReg = 0;
|
|
|
|
if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
|
|
|
|
TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
|
|
|
|
TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
|
|
|
|
ResultReg = createResultReg(DstClass);
|
|
|
|
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
|
|
Op0, DstClass, SrcClass);
|
|
|
|
if (!InsertedCopy)
|
|
|
|
ResultReg = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the reg-reg copy failed, select a BIT_CONVERT opcode.
|
|
|
|
if (!ResultReg)
|
|
|
|
ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
|
|
|
|
ISD::BIT_CONVERT, Op0);
|
|
|
|
|
|
|
|
if (!ResultReg)
|
2008-08-26 23:46:32 +00:00
|
|
|
return false;
|
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
UpdateValueMap(I, ResultReg);
|
2008-08-26 23:46:32 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
bool
|
|
|
|
FastISel::SelectInstruction(Instruction *I) {
|
2008-09-05 18:18:20 +00:00
|
|
|
return SelectOperator(I, I->getOpcode());
|
|
|
|
}
|
|
|
|
|
2008-10-02 22:15:21 +00:00
|
|
|
/// FastEmitBranch - Emit an unconditional branch to the given block,
|
|
|
|
/// unless it is the immediate (fall-through) successor, and update
|
|
|
|
/// the CFG.
|
|
|
|
void
|
|
|
|
FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
|
|
|
|
MachineFunction::iterator NextMBB =
|
|
|
|
next(MachineFunction::iterator(MBB));
|
|
|
|
|
|
|
|
if (MBB->isLayoutSuccessor(MSucc)) {
|
|
|
|
// The unconditional fall-through case, which needs no instructions.
|
|
|
|
} else {
|
|
|
|
// The unconditional branch case.
|
|
|
|
TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
|
|
|
|
}
|
|
|
|
MBB->addSuccessor(MSucc);
|
|
|
|
}
|
|
|
|
|
2008-09-05 18:18:20 +00:00
|
|
|
bool
|
|
|
|
FastISel::SelectOperator(User *I, unsigned Opcode) {
|
|
|
|
switch (Opcode) {
|
2008-09-03 23:12:08 +00:00
|
|
|
case Instruction::Add: {
|
|
|
|
ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
|
|
|
|
return SelectBinaryOp(I, Opc);
|
|
|
|
}
|
|
|
|
case Instruction::Sub: {
|
|
|
|
ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
|
|
|
|
return SelectBinaryOp(I, Opc);
|
|
|
|
}
|
|
|
|
case Instruction::Mul: {
|
|
|
|
ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
|
|
|
|
return SelectBinaryOp(I, Opc);
|
|
|
|
}
|
|
|
|
case Instruction::SDiv:
|
|
|
|
return SelectBinaryOp(I, ISD::SDIV);
|
|
|
|
case Instruction::UDiv:
|
|
|
|
return SelectBinaryOp(I, ISD::UDIV);
|
|
|
|
case Instruction::FDiv:
|
|
|
|
return SelectBinaryOp(I, ISD::FDIV);
|
|
|
|
case Instruction::SRem:
|
|
|
|
return SelectBinaryOp(I, ISD::SREM);
|
|
|
|
case Instruction::URem:
|
|
|
|
return SelectBinaryOp(I, ISD::UREM);
|
|
|
|
case Instruction::FRem:
|
|
|
|
return SelectBinaryOp(I, ISD::FREM);
|
|
|
|
case Instruction::Shl:
|
|
|
|
return SelectBinaryOp(I, ISD::SHL);
|
|
|
|
case Instruction::LShr:
|
|
|
|
return SelectBinaryOp(I, ISD::SRL);
|
|
|
|
case Instruction::AShr:
|
|
|
|
return SelectBinaryOp(I, ISD::SRA);
|
|
|
|
case Instruction::And:
|
|
|
|
return SelectBinaryOp(I, ISD::AND);
|
|
|
|
case Instruction::Or:
|
|
|
|
return SelectBinaryOp(I, ISD::OR);
|
|
|
|
case Instruction::Xor:
|
|
|
|
return SelectBinaryOp(I, ISD::XOR);
|
|
|
|
|
|
|
|
case Instruction::GetElementPtr:
|
|
|
|
return SelectGetElementPtr(I);
|
|
|
|
|
|
|
|
case Instruction::Br: {
|
|
|
|
BranchInst *BI = cast<BranchInst>(I);
|
|
|
|
|
|
|
|
if (BI->isUnconditional()) {
|
|
|
|
BasicBlock *LLVMSucc = BI->getSuccessor(0);
|
|
|
|
MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
|
2008-10-02 22:15:21 +00:00
|
|
|
FastEmitBranch(MSucc);
|
2008-09-03 23:12:08 +00:00
|
|
|
return true;
|
2008-08-27 00:31:01 +00:00
|
|
|
}
|
2008-09-03 23:12:08 +00:00
|
|
|
|
|
|
|
// Conditional branches are not handed yet.
|
|
|
|
// Halt "fast" selection and bail.
|
|
|
|
return false;
|
2008-08-13 20:19:35 +00:00
|
|
|
}
|
|
|
|
|
2008-09-05 01:08:41 +00:00
|
|
|
case Instruction::Unreachable:
|
|
|
|
// Nothing to emit.
|
|
|
|
return true;
|
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
case Instruction::PHI:
|
|
|
|
// PHI nodes are already emitted.
|
|
|
|
return true;
|
2008-09-10 20:11:02 +00:00
|
|
|
|
|
|
|
case Instruction::Alloca:
|
|
|
|
// FunctionLowering has the static-sized case covered.
|
|
|
|
if (StaticAllocaMap.count(cast<AllocaInst>(I)))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Dynamic-sized alloca is not handled yet.
|
|
|
|
return false;
|
2008-09-03 23:12:08 +00:00
|
|
|
|
2008-09-25 17:05:24 +00:00
|
|
|
case Instruction::Call:
|
|
|
|
return SelectCall(I);
|
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
case Instruction::BitCast:
|
|
|
|
return SelectBitCast(I);
|
|
|
|
|
|
|
|
case Instruction::FPToSI:
|
|
|
|
return SelectCast(I, ISD::FP_TO_SINT);
|
|
|
|
case Instruction::ZExt:
|
|
|
|
return SelectCast(I, ISD::ZERO_EXTEND);
|
|
|
|
case Instruction::SExt:
|
|
|
|
return SelectCast(I, ISD::SIGN_EXTEND);
|
|
|
|
case Instruction::Trunc:
|
|
|
|
return SelectCast(I, ISD::TRUNCATE);
|
|
|
|
case Instruction::SIToFP:
|
|
|
|
return SelectCast(I, ISD::SINT_TO_FP);
|
|
|
|
|
|
|
|
case Instruction::IntToPtr: // Deliberate fall-through.
|
|
|
|
case Instruction::PtrToInt: {
|
|
|
|
MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
|
|
|
|
MVT DstVT = TLI.getValueType(I->getType());
|
|
|
|
if (DstVT.bitsGT(SrcVT))
|
|
|
|
return SelectCast(I, ISD::ZERO_EXTEND);
|
|
|
|
if (DstVT.bitsLT(SrcVT))
|
|
|
|
return SelectCast(I, ISD::TRUNCATE);
|
|
|
|
unsigned Reg = getRegForValue(I->getOperand(0));
|
|
|
|
if (Reg == 0) return false;
|
|
|
|
UpdateValueMap(I, Reg);
|
|
|
|
return true;
|
|
|
|
}
|
2008-09-23 21:53:34 +00:00
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
default:
|
|
|
|
// Unhandled instruction. Halt "fast" selection and bail.
|
|
|
|
return false;
|
|
|
|
}
|
2008-08-13 20:19:35 +00:00
|
|
|
}
|
|
|
|
|
2008-09-03 23:12:08 +00:00
|
|
|
FastISel::FastISel(MachineFunction &mf,
|
2008-09-23 21:53:34 +00:00
|
|
|
MachineModuleInfo *mmi,
|
2008-09-03 23:12:08 +00:00
|
|
|
DenseMap<const Value *, unsigned> &vm,
|
2008-09-10 20:11:02 +00:00
|
|
|
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
|
|
|
|
DenseMap<const AllocaInst *, int> &am)
|
2008-09-03 23:12:08 +00:00
|
|
|
: MBB(0),
|
|
|
|
ValueMap(vm),
|
|
|
|
MBBMap(bm),
|
2008-09-10 20:11:02 +00:00
|
|
|
StaticAllocaMap(am),
|
2008-09-03 23:12:08 +00:00
|
|
|
MF(mf),
|
2008-09-23 21:53:34 +00:00
|
|
|
MMI(mmi),
|
2008-09-03 23:12:08 +00:00
|
|
|
MRI(MF.getRegInfo()),
|
2008-09-10 20:11:02 +00:00
|
|
|
MFI(*MF.getFrameInfo()),
|
|
|
|
MCP(*MF.getConstantPool()),
|
2008-09-03 23:12:08 +00:00
|
|
|
TM(MF.getTarget()),
|
2008-08-22 00:20:26 +00:00
|
|
|
TD(*TM.getTargetData()),
|
|
|
|
TII(*TM.getInstrInfo()),
|
|
|
|
TLI(*TM.getTargetLowering()) {
|
2008-08-20 21:05:57 +00:00
|
|
|
}
|
|
|
|
|
2008-08-14 21:51:29 +00:00
|
|
|
FastISel::~FastISel() {}
|
|
|
|
|
2008-09-02 21:59:13 +00:00
|
|
|
unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
|
|
ISD::NodeType) {
|
2008-08-13 20:19:35 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-08-25 23:58:18 +00:00
|
|
|
unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
|
|
ISD::NodeType, unsigned /*Op0*/) {
|
2008-08-13 20:19:35 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-08-25 23:58:18 +00:00
|
|
|
unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
|
|
ISD::NodeType, unsigned /*Op0*/,
|
|
|
|
unsigned /*Op0*/) {
|
2008-08-13 20:19:35 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-08-25 23:58:18 +00:00
|
|
|
unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
|
|
ISD::NodeType, uint64_t /*Imm*/) {
|
2008-08-20 22:45:34 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-08-27 01:09:54 +00:00
|
|
|
unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
|
|
ISD::NodeType, ConstantFP * /*FPImm*/) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-08-25 23:58:18 +00:00
|
|
|
unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
|
|
ISD::NodeType, unsigned /*Op0*/,
|
|
|
|
uint64_t /*Imm*/) {
|
2008-08-21 01:41:07 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-08-27 01:09:54 +00:00
|
|
|
unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
|
|
ISD::NodeType, unsigned /*Op0*/,
|
|
|
|
ConstantFP * /*FPImm*/) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-08-25 23:58:18 +00:00
|
|
|
unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
|
|
|
|
ISD::NodeType,
|
2008-08-21 01:41:07 +00:00
|
|
|
unsigned /*Op0*/, unsigned /*Op1*/,
|
|
|
|
uint64_t /*Imm*/) {
|
2008-08-20 22:45:34 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
|
|
|
|
/// to emit an instruction with an immediate operand using FastEmit_ri.
|
|
|
|
/// If that fails, it materializes the immediate into a register and try
|
|
|
|
/// FastEmit_rr instead.
|
|
|
|
unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
|
2008-08-21 01:41:07 +00:00
|
|
|
unsigned Op0, uint64_t Imm,
|
|
|
|
MVT::SimpleValueType ImmType) {
|
2008-08-20 22:45:34 +00:00
|
|
|
// First check if immediate type is legal. If not, we can't use the ri form.
|
2008-08-27 18:15:05 +00:00
|
|
|
unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
|
2008-08-20 22:45:34 +00:00
|
|
|
if (ResultReg != 0)
|
|
|
|
return ResultReg;
|
2008-08-25 23:58:18 +00:00
|
|
|
unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
|
2008-08-21 01:41:07 +00:00
|
|
|
if (MaterialReg == 0)
|
|
|
|
return 0;
|
2008-08-25 23:58:18 +00:00
|
|
|
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
|
2008-08-21 01:41:07 +00:00
|
|
|
}
|
|
|
|
|
2008-08-27 01:09:54 +00:00
|
|
|
/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
|
|
|
|
/// to emit an instruction with a floating-point immediate operand using
|
|
|
|
/// FastEmit_rf. If that fails, it materializes the immediate into a register
|
|
|
|
/// and try FastEmit_rr instead.
|
|
|
|
unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
|
|
|
|
unsigned Op0, ConstantFP *FPImm,
|
|
|
|
MVT::SimpleValueType ImmType) {
|
|
|
|
// First check if immediate type is legal. If not, we can't use the rf form.
|
2008-08-27 18:15:05 +00:00
|
|
|
unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
|
2008-08-27 01:09:54 +00:00
|
|
|
if (ResultReg != 0)
|
|
|
|
return ResultReg;
|
|
|
|
|
|
|
|
// Materialize the constant in a register.
|
|
|
|
unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
|
|
|
|
if (MaterialReg == 0) {
|
2008-08-27 18:01:42 +00:00
|
|
|
// If the target doesn't have a way to directly enter a floating-point
|
|
|
|
// value into a register, use an alternate approach.
|
|
|
|
// TODO: The current approach only supports floating-point constants
|
|
|
|
// that can be constructed by conversion from integer values. This should
|
|
|
|
// be replaced by code that creates a load from a constant-pool entry,
|
|
|
|
// which will require some target-specific work.
|
2008-08-27 01:09:54 +00:00
|
|
|
const APFloat &Flt = FPImm->getValueAPF();
|
|
|
|
MVT IntVT = TLI.getPointerTy();
|
|
|
|
|
|
|
|
uint64_t x[2];
|
|
|
|
uint32_t IntBitWidth = IntVT.getSizeInBits();
|
2008-10-09 23:00:39 +00:00
|
|
|
bool isExact;
|
|
|
|
(void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
|
|
|
|
APFloat::rmTowardZero, &isExact);
|
|
|
|
if (!isExact)
|
2008-08-27 01:09:54 +00:00
|
|
|
return 0;
|
|
|
|
APInt IntVal(IntBitWidth, 2, x);
|
|
|
|
|
|
|
|
unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
|
|
|
|
ISD::Constant, IntVal.getZExtValue());
|
|
|
|
if (IntegerReg == 0)
|
|
|
|
return 0;
|
|
|
|
MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
|
|
|
|
ISD::SINT_TO_FP, IntegerReg);
|
|
|
|
if (MaterialReg == 0)
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
|
|
|
|
}
|
|
|
|
|
2008-08-21 01:41:07 +00:00
|
|
|
unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
|
|
|
|
return MRI.createVirtualRegister(RC);
|
2008-08-20 22:45:34 +00:00
|
|
|
}
|
|
|
|
|
2008-08-13 20:19:35 +00:00
|
|
|
unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
|
2008-08-20 18:09:38 +00:00
|
|
|
const TargetRegisterClass* RC) {
|
2008-08-21 01:41:07 +00:00
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2008-08-20 21:05:57 +00:00
|
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
2008-08-13 20:19:35 +00:00
|
|
|
|
2008-08-20 23:53:10 +00:00
|
|
|
BuildMI(MBB, II, ResultReg);
|
2008-08-13 20:19:35 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0) {
|
2008-08-21 01:41:07 +00:00
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2008-08-20 21:05:57 +00:00
|
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
2008-08-13 20:19:35 +00:00
|
|
|
|
2008-09-08 08:38:20 +00:00
|
|
|
if (II.getNumDefs() >= 1)
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0);
|
|
|
|
else {
|
|
|
|
BuildMI(MBB, II).addReg(Op0);
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
|
|
II.ImplicitDefs[0], RC, RC);
|
|
|
|
if (!InsertedCopy)
|
|
|
|
ResultReg = 0;
|
|
|
|
}
|
|
|
|
|
2008-08-13 20:19:35 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, unsigned Op1) {
|
2008-08-21 01:41:07 +00:00
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2008-08-20 21:05:57 +00:00
|
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
2008-08-13 20:19:35 +00:00
|
|
|
|
2008-09-08 08:38:20 +00:00
|
|
|
if (II.getNumDefs() >= 1)
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
|
|
|
|
else {
|
|
|
|
BuildMI(MBB, II).addReg(Op0).addReg(Op1);
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
|
|
II.ImplicitDefs[0], RC, RC);
|
|
|
|
if (!InsertedCopy)
|
|
|
|
ResultReg = 0;
|
|
|
|
}
|
2008-08-13 20:19:35 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
2008-08-21 01:41:07 +00:00
|
|
|
|
|
|
|
unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, uint64_t Imm) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
|
2008-09-08 08:38:20 +00:00
|
|
|
if (II.getNumDefs() >= 1)
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
|
|
|
|
else {
|
|
|
|
BuildMI(MBB, II).addReg(Op0).addImm(Imm);
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
|
|
II.ImplicitDefs[0], RC, RC);
|
|
|
|
if (!InsertedCopy)
|
|
|
|
ResultReg = 0;
|
|
|
|
}
|
2008-08-21 01:41:07 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
2008-08-27 01:09:54 +00:00
|
|
|
unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, ConstantFP *FPImm) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
|
2008-09-08 08:38:20 +00:00
|
|
|
if (II.getNumDefs() >= 1)
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
|
|
|
|
else {
|
|
|
|
BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm);
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
|
|
II.ImplicitDefs[0], RC, RC);
|
|
|
|
if (!InsertedCopy)
|
|
|
|
ResultReg = 0;
|
|
|
|
}
|
2008-08-27 01:09:54 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
2008-08-21 01:41:07 +00:00
|
|
|
unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, unsigned Op1, uint64_t Imm) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
|
2008-09-08 08:38:20 +00:00
|
|
|
if (II.getNumDefs() >= 1)
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
|
|
|
|
else {
|
|
|
|
BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm);
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
|
|
II.ImplicitDefs[0], RC, RC);
|
|
|
|
if (!InsertedCopy)
|
|
|
|
ResultReg = 0;
|
|
|
|
}
|
2008-08-21 01:41:07 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
2008-08-25 20:20:32 +00:00
|
|
|
|
|
|
|
unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
uint64_t Imm) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
|
|
|
|
|
2008-09-08 08:38:20 +00:00
|
|
|
if (II.getNumDefs() >= 1)
|
|
|
|
BuildMI(MBB, II, ResultReg).addImm(Imm);
|
|
|
|
else {
|
|
|
|
BuildMI(MBB, II).addImm(Imm);
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
|
|
II.ImplicitDefs[0], RC, RC);
|
|
|
|
if (!InsertedCopy)
|
|
|
|
ResultReg = 0;
|
|
|
|
}
|
2008-08-25 20:20:32 +00:00
|
|
|
return ResultReg;
|
2008-08-25 22:20:39 +00:00
|
|
|
}
|
2008-08-27 22:30:02 +00:00
|
|
|
|
2008-08-28 17:47:37 +00:00
|
|
|
unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
|
|
|
|
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
|
2008-08-27 22:30:02 +00:00
|
|
|
const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
|
|
|
|
|
|
|
|
unsigned ResultReg = createResultReg(SRC);
|
|
|
|
const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
|
|
|
|
|
2008-09-08 08:38:20 +00:00
|
|
|
if (II.getNumDefs() >= 1)
|
|
|
|
BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
|
|
|
|
else {
|
|
|
|
BuildMI(MBB, II).addReg(Op0).addImm(Idx);
|
|
|
|
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
|
|
|
|
II.ImplicitDefs[0], RC, RC);
|
|
|
|
if (!InsertedCopy)
|
|
|
|
ResultReg = 0;
|
|
|
|
}
|
2008-08-27 22:30:02 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|