llvm-6502/test/CodeGen/ARM64/vector-ext.ll

; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s

;CHECK: @func30
;CHECK: ushll.4s  v0, v0, #0
;CHECK: movi.4s v1, #0x1
;CHECK: and.16b v0, v0, v1
;CHECK: str  q0, [x0]
;CHECK: ret

%T0_30 = type <4 x i1>
%T1_30 = type <4 x i32>
define void @func30(%T0_30 %v0, %T1_30* %p1) {
  %r = zext %T0_30 %v0 to %T1_30
  store %T1_30 %r, %T1_30* %p1
  ret void
}
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8 2014-03-29 10:18:08 +00:00			`; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple \| FileCheck %s`

			`;CHECK: @func30`
			`;CHECK: ushll.4s v0, v0, #0`
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8 2014-04-30 11:19:28 +00:00			`;CHECK: movi.4s v1, #0x1`
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8 2014-03-29 10:18:08 +00:00			`;CHECK: and.16b v0, v0, v1`
			`;CHECK: str q0, [x0]`
			`;CHECK: ret`

			`%T0_30 = type <4 x i1>`
			`%T1_30 = type <4 x i32>`
			`define void @func30(%T0_30 %v0, %T1_30* %p1) {`
			`%r = zext %T0_30 %v0 to %T1_30`
			`store %T1_30 %r, %T1_30* %p1`
			`ret void`
			`}`