2013-08-28 10:02:29 +00:00
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; Test the MSA floating-point conversion intrinsics that are encoded with the
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; 3RF instruction format.
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2013-09-27 10:08:31 +00:00
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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[Mips][msa] Added the simple builtins (fadd to ftq)
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 13:45:36 +00:00
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@llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_fexdo_h_RES = global <8 x half> <half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00>, align 16
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define void @llvm_mips_fexdo_h_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fexdo_h_ARG1
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%1 = load <4 x float>* @llvm_mips_fexdo_h_ARG2
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%2 = tail call <8 x half> @llvm.mips.fexdo.h(<4 x float> %0, <4 x float> %1)
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store <8 x half> %2, <8 x half>* @llvm_mips_fexdo_h_RES
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ret void
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}
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declare <8 x half> @llvm.mips.fexdo.h(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_fexdo_h_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fexdo.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_fexdo_h_test
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;
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@llvm_mips_fexdo_w_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_fexdo_w_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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@llvm_mips_fexdo_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fexdo_w_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fexdo_w_ARG1
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%1 = load <2 x double>* @llvm_mips_fexdo_w_ARG2
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%2 = tail call <4 x float> @llvm.mips.fexdo.w(<2 x double> %0, <2 x double> %1)
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store <4 x float> %2, <4 x float>* @llvm_mips_fexdo_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fexdo.w(<2 x double>, <2 x double>) nounwind
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; CHECK: llvm_mips_fexdo_w_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fexdo.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fexdo_w_test
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;
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