llvm-6502/test/CodeGen/X86/constant-pool-remat-0.ll

; RUN: llvm-as < %s | llc -march=x86-64 | grep LCPI | count 3
; RUN: llvm-as < %s | llc -march=x86-64 -stats  -info-output-file - | grep asm-printer | grep 6
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep LCPI | count 3
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats  -info-output-file - | grep asm-printer | grep 12

declare float @qux(float %y)

define float @array(float %a) nounwind {
  %n = fmul float %a, 9.0
  %m = call float @qux(float %n)
  %o = fmul float %m, 9.0
  ret float %o
}
switch this to use fastcc to avoid fpstack traffic on x86-32. Switch to using the count script instead of wc -l git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41072 91177308-0d34-0410-b5e6-96231b3b80d8 2007-08-14 16:14:10 +00:00			`; RUN: llvm-as < %s \| llc -march=x86-64 \| grep LCPI \| count 3`
Remove -unwind-tables-optional everywhere, since this is now the default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49667 91177308-0d34-0410-b5e6-96231b3b80d8 2008-04-14 17:56:54 +00:00			`; RUN: llvm-as < %s \| llc -march=x86-64 -stats -info-output-file - \| grep asm-printer \| grep 6`
switch this to use fastcc to avoid fpstack traffic on x86-32. Switch to using the count script instead of wc -l git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41072 91177308-0d34-0410-b5e6-96231b3b80d8 2007-08-14 16:14:10 +00:00			`; RUN: llvm-as < %s \| llc -march=x86 -mattr=+sse2 \| grep LCPI \| count 3`
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-05 17:24:07 +00:00			`; RUN: llvm-as < %s \| llc -march=x86 -mattr=+sse2 -stats -info-output-file - \| grep asm-printer \| grep 12`
Mark the SSE and MMX load instructions that X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle with the isReMaterializable flag so that it is given a chance to handle them. Without hoisting constant-pool loads from loops this isn't very visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from making a copy of the constant pool on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8 2007-08-02 14:27:55 +00:00
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-05 17:24:07 +00:00			`declare float @qux(float %y)`
Mark the SSE and MMX load instructions that X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle with the isReMaterializable flag so that it is given a chance to handle them. Without hoisting constant-pool loads from loops this isn't very visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from making a copy of the constant pool on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8 2007-08-02 14:27:55 +00:00
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-05 17:24:07 +00:00			`define float @array(float %a) nounwind {`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-04 22:49:04 +00:00			`%n = fmul float %a, 9.0`
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8 2008-09-05 17:24:07 +00:00			`%m = call float @qux(float %n)`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-04 22:49:04 +00:00			`%o = fmul float %m, 9.0`
Mark the SSE and MMX load instructions that X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle with the isReMaterializable flag so that it is given a chance to handle them. Without hoisting constant-pool loads from loops this isn't very visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from making a copy of the constant pool on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8 2007-08-02 14:27:55 +00:00			`ret float %o`
			`}`