llvm-6502/test/CodeGen/X86/widen_conv-1.ll

; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: paddq

; truncate v2i64 to v2i32

define void @convert(<2 x i32>* %dst.addr, <2 x i64> %src) nounwind {
entry:
	%val = trunc <2 x i64> %src to <2 x i32>
	%add = add <2 x i32> %val, < i32 1, i32 1 >
	store <2 x i32> %add, <2 x i32>* %dst.addr
	ret void
}
now that generic vector types aren't selected onto MMX registers, these tests don't need -disable-mmx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122188 91177308-0d34-0410-b5e6-96231b3b80d8 2010-12-19 20:12:58 +00:00			`; RUN: llc < %s -march=x86 -mattr=+sse42 \| FileCheck %s`
Enable element promotion type legalization by deafault. Changed tests which assumed that vectors are legalized by widening them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8 2011-10-16 20:31:33 +00:00			`; CHECK: paddq`
Added some basic test cases for r61209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61210 91177308-0d34-0410-b5e6-96231b3b80d8 2008-12-18 20:05:58 +00:00
			`; truncate v2i64 to v2i32`

			`define void @convert(<2 x i32>* %dst.addr, <2 x i64> %src) nounwind {`
			`entry:`
			`%val = trunc <2 x i64> %src to <2 x i32>`
			`%add = add <2 x i32> %val, < i32 1, i32 1 >`
			`store <2 x i32> %add, <2 x i32>* %dst.addr`
			`ret void`
			`}`