2012-07-31 21:49:49 +00:00
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//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16InstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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2012-12-03 16:50:05 +00:00
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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2012-07-31 21:49:49 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2013-02-08 03:57:41 +00:00
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#include "llvm/CodeGen/RegisterScavenging.h"
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2013-11-13 04:37:52 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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2012-12-20 04:07:42 +00:00
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#include "llvm/Support/CommandLine.h"
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2013-02-18 00:59:04 +00:00
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#include "llvm/Support/Debug.h"
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2012-07-31 21:49:49 +00:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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2013-11-13 06:27:53 +00:00
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#include <cctype>
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2012-07-31 21:49:49 +00:00
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using namespace llvm;
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2014-04-21 22:55:11 +00:00
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#define DEBUG_TYPE "mips16-instrinfo"
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2012-12-20 04:07:42 +00:00
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2014-07-18 23:25:00 +00:00
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Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)
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2015-03-12 05:43:57 +00:00
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: MipsInstrInfo(STI, Mips::Bimm16), RI() {}
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2012-07-31 23:41:32 +00:00
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const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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return RI;
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}
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2012-07-31 21:49:49 +00:00
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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2014-07-18 22:34:14 +00:00
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unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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2012-07-31 21:49:49 +00:00
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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2014-07-18 22:34:14 +00:00
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unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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2012-07-31 21:49:49 +00:00
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return 0;
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}
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void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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2012-10-12 02:01:09 +00:00
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.contains(DestReg) &&
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2013-08-06 23:08:38 +00:00
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Mips::GPR32RegClass.contains(SrcReg))
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2012-10-12 02:01:09 +00:00
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Opc = Mips::MoveR3216;
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2013-08-06 23:08:38 +00:00
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else if (Mips::GPR32RegClass.contains(DestReg) &&
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2012-10-12 02:01:09 +00:00
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Mips::CPU16RegsRegClass.contains(SrcReg))
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Opc = Mips::Move32R16;
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2013-08-14 00:47:08 +00:00
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else if ((SrcReg == Mips::HI0) &&
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2012-10-12 02:01:09 +00:00
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mfhi16, SrcReg = 0;
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2013-08-14 00:47:08 +00:00
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else if ((SrcReg == Mips::LO0) &&
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2012-10-12 02:01:09 +00:00
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mflo16, SrcReg = 0;
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2012-07-31 21:49:49 +00:00
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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}
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2014-07-18 22:34:14 +00:00
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void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const {
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2012-09-28 02:26:24 +00:00
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::SwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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2013-08-04 01:13:25 +00:00
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
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addFrameIndex(FI).addImm(Offset)
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.addMemOperand(MMO);
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2012-07-31 21:49:49 +00:00
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}
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2014-07-18 22:34:14 +00:00
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void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const {
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2012-09-28 02:26:24 +00:00
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::LwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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2013-03-29 02:14:12 +00:00
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BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
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2012-09-28 02:26:24 +00:00
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.addMemOperand(MMO);
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2012-07-31 21:49:49 +00:00
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}
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bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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MachineBasicBlock &MBB = *MI->getParent();
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switch(MI->getDesc().getOpcode()) {
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default:
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return false;
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case Mips::RetRA16:
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2012-10-30 00:54:49 +00:00
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ExpandRetRA16(MBB, MI, Mips::JrcRa16);
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2012-07-31 21:49:49 +00:00
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break;
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}
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MBB.erase(MI);
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return true;
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}
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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2013-05-13 17:43:19 +00:00
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unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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2012-10-17 22:29:54 +00:00
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switch (Opc) {
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case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
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case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
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2013-11-15 02:21:52 +00:00
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case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
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case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
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2012-10-17 22:29:54 +00:00
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case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
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case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
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case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
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2013-11-15 02:21:52 +00:00
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case Mips::Btnez16: return Mips::Bteqz16;
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2012-10-17 22:29:54 +00:00
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case Mips::BtnezX16: return Mips::BteqzX16;
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case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
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case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
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case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
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2013-11-15 02:21:52 +00:00
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case Mips::Bteqz16: return Mips::Btnez16;
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2012-10-17 22:29:54 +00:00
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case Mips::BteqzX16: return Mips::BtnezX16;
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case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
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case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
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case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
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case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
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case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
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case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
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}
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2015-01-05 10:15:49 +00:00
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llvm_unreachable("Illegal opcode!");
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2012-07-31 21:49:49 +00:00
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}
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2013-12-15 20:49:30 +00:00
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static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
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2014-07-18 22:34:14 +00:00
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const std::vector<CalleeSavedInfo> &CSI,
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unsigned Flags = 0) {
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2013-12-15 20:49:30 +00:00
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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// Add the callee-saved register as live-in. Do not add if the register is
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// RA and return address is taken, because it has already been added in
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// method MipsTargetLowering::LowerRETURNADDR.
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// It's killed at the spill, unless the register is RA and return address
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// is taken.
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unsigned Reg = CSI[e-i-1].getReg();
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switch (Reg) {
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case Mips::RA:
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case Mips::S0:
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case Mips::S1:
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MIB.addReg(Reg, Flags);
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break;
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case Mips::S2:
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break;
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default:
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llvm_unreachable("unexpected mips16 callee saved register");
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}
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}
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}
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2012-12-20 04:07:42 +00:00
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// Adjust SP by FrameSize bytes. Save RA, S0, S1
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2013-01-19 02:00:40 +00:00
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void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
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2014-07-18 22:34:14 +00:00
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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2012-12-20 04:07:42 +00:00
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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2013-12-15 20:49:30 +00:00
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const BitVector Reserved = RI.getReservedRegs(MF);
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2013-12-10 14:29:38 +00:00
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bool SaveS2 = Reserved[Mips::S2];
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MachineInstrBuilder MIB;
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2013-12-11 03:32:44 +00:00
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unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
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2013-12-15 20:49:30 +00:00
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MIB = BuildMI(MBB, I, DL, get(Opc));
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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addSaveRestoreRegs(MIB, CSI);
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if (SaveS2)
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MIB.addReg(Mips::S2);
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2013-12-09 21:19:51 +00:00
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if (isUInt<11>(FrameSize))
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2013-12-15 20:49:30 +00:00
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MIB.addImm(FrameSize);
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2012-12-20 04:07:42 +00:00
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else {
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2013-12-09 21:19:51 +00:00
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int Base = 2040; // should create template function like isUInt that
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// returns largest possible n bit unsigned integer
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int64_t Remainder = FrameSize - Base;
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2013-12-15 20:49:30 +00:00
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MIB.addImm(Base);
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2013-12-09 21:19:51 +00:00
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if (isInt<16>(-Remainder))
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BuildAddiuSpImm(MBB, I, -Remainder);
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else
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adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
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2012-12-20 04:07:42 +00:00
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}
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}
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// Adjust SP by FrameSize bytes. Restore RA, S0, S1
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2013-01-19 02:00:40 +00:00
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void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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2012-12-20 04:07:42 +00:00
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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2013-12-15 20:49:30 +00:00
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MachineFunction *MF = MBB.getParent();
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MachineFrameInfo *MFI = MF->getFrameInfo();
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const BitVector Reserved = RI.getReservedRegs(*MF);
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2013-12-10 14:29:38 +00:00
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bool SaveS2 = Reserved[Mips::S2];
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MachineInstrBuilder MIB;
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2013-12-11 03:32:44 +00:00
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unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
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Mips::Restore16:Mips::RestoreX16;
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2013-12-15 20:49:30 +00:00
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if (!isUInt<11>(FrameSize)) {
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unsigned Base = 2040;
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2013-12-09 21:19:51 +00:00
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int64_t Remainder = FrameSize - Base;
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2013-12-15 20:49:30 +00:00
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FrameSize = Base; // should create template function like isUInt that
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// returns largest possible n bit unsigned integer
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2013-12-09 21:19:51 +00:00
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if (isInt<16>(Remainder))
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BuildAddiuSpImm(MBB, I, Remainder);
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else
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adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
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2012-12-20 04:07:42 +00:00
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}
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2013-12-15 20:49:30 +00:00
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MIB = BuildMI(MBB, I, DL, get(Opc));
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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addSaveRestoreRegs(MIB, CSI, RegState::Define);
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2013-12-10 14:29:38 +00:00
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if (SaveS2)
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MIB.addReg(Mips::S2, RegState::Define);
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2013-12-15 20:49:30 +00:00
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MIB.addImm(FrameSize);
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2012-12-20 04:07:42 +00:00
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}
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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2013-01-19 02:00:40 +00:00
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// This can only be called at times that we know that there is at least one free
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// register.
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2012-12-20 04:07:42 +00:00
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// This is clearly safe at prologue and epilogue.
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//
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2013-01-19 02:00:40 +00:00
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void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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2012-12-20 04:07:42 +00:00
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MachineBasicBlock::iterator I,
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unsigned Reg1, unsigned Reg2) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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//
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// li reg1, constant
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// move reg2, sp
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// add reg1, reg1, reg2
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// move sp, reg1
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//
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//
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|
|
MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
|
2013-11-24 06:18:50 +00:00
|
|
|
MIB1.addImm(Amount).addImm(-1);
|
2012-12-20 04:07:42 +00:00
|
|
|
MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
|
|
|
|
MIB2.addReg(Mips::SP, RegState::Kill);
|
|
|
|
MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
|
|
|
|
MIB3.addReg(Reg1);
|
|
|
|
MIB3.addReg(Reg2, RegState::Kill);
|
2013-01-19 02:00:40 +00:00
|
|
|
MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
|
|
|
|
Mips::SP);
|
2012-12-20 04:07:42 +00:00
|
|
|
MIB4.addReg(Reg1, RegState::Kill);
|
|
|
|
}
|
|
|
|
|
2014-07-18 22:34:14 +00:00
|
|
|
void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
|
|
|
|
unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) const {
|
2015-01-05 10:15:49 +00:00
|
|
|
llvm_unreachable("adjust stack pointer amount exceeded");
|
2012-12-20 04:07:42 +00:00
|
|
|
}
|
|
|
|
|
2012-10-31 05:21:10 +00:00
|
|
|
/// Adjust SP by Amount bytes.
|
|
|
|
void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
|
|
|
|
MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) const {
|
2012-12-20 04:07:42 +00:00
|
|
|
if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
|
2013-02-16 19:04:29 +00:00
|
|
|
BuildAddiuSpImm(MBB, I, Amount);
|
2012-10-31 05:21:10 +00:00
|
|
|
else
|
2012-12-20 04:07:42 +00:00
|
|
|
adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// This function generates the sequence of instructions needed to get the
|
|
|
|
/// result of adding register REG and immediate IMM.
|
2014-07-18 22:34:14 +00:00
|
|
|
unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
|
|
|
|
MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator II,
|
|
|
|
DebugLoc DL, unsigned &NewImm) const {
|
2013-02-08 03:57:41 +00:00
|
|
|
//
|
|
|
|
// given original instruction is:
|
|
|
|
// Instr rx, T[offset] where offset is too big.
|
|
|
|
//
|
|
|
|
// lo = offset & 0xFFFF
|
|
|
|
// hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
|
|
|
|
//
|
|
|
|
// let T = temporary register
|
|
|
|
// li T, hi
|
|
|
|
// shl T, 16
|
|
|
|
// add T, Rx, T
|
|
|
|
//
|
|
|
|
RegScavenger rs;
|
|
|
|
int32_t lo = Imm & 0xFFFF;
|
|
|
|
NewImm = lo;
|
2013-08-04 01:13:25 +00:00
|
|
|
int Reg =0;
|
|
|
|
int SpReg = 0;
|
|
|
|
|
2013-02-08 03:57:41 +00:00
|
|
|
rs.enterBasicBlock(&MBB);
|
|
|
|
rs.forward(II);
|
|
|
|
//
|
2013-08-04 01:13:25 +00:00
|
|
|
// We need to know which registers can be used, in the case where there
|
|
|
|
// are not enough free registers. We exclude all registers that
|
|
|
|
// are used in the instruction that we are helping.
|
|
|
|
// // Consider all allocatable registers in the register class initially
|
|
|
|
BitVector Candidates =
|
|
|
|
RI.getAllocatableSet
|
|
|
|
(*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
|
|
|
|
// Exclude all the registers being used by the instruction.
|
|
|
|
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = II->getOperand(i);
|
|
|
|
if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
|
|
|
|
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
|
|
|
Candidates.reset(MO.getReg());
|
|
|
|
}
|
2014-07-18 22:34:14 +00:00
|
|
|
|
2013-08-04 01:13:25 +00:00
|
|
|
// If the same register was used and defined in an instruction, then
|
|
|
|
// it will not be in the list of candidates.
|
|
|
|
//
|
|
|
|
// we need to analyze the instruction that we are helping.
|
|
|
|
// we need to know if it defines register x but register x is not
|
|
|
|
// present as an operand of the instruction. this tells
|
|
|
|
// whether the register is live before the instruction. if it's not
|
|
|
|
// then we don't need to save it in case there are no free registers.
|
|
|
|
int DefReg = 0;
|
|
|
|
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = II->getOperand(i);
|
|
|
|
if (MO.isReg() && MO.isDef()) {
|
|
|
|
DefReg = MO.getReg();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-18 22:34:14 +00:00
|
|
|
BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
|
2013-08-04 01:13:25 +00:00
|
|
|
Available &= Candidates;
|
|
|
|
//
|
2013-02-08 03:57:41 +00:00
|
|
|
// we use T0 for the first register, if we need to save something away.
|
|
|
|
// we use T1 for the second register, if we need to save something away.
|
|
|
|
//
|
|
|
|
unsigned FirstRegSaved =0, SecondRegSaved=0;
|
|
|
|
unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
|
|
|
|
|
2013-08-04 01:13:25 +00:00
|
|
|
Reg = Available.find_first();
|
|
|
|
|
|
|
|
if (Reg == -1) {
|
|
|
|
Reg = Candidates.find_first();
|
|
|
|
Candidates.reset(Reg);
|
|
|
|
if (DefReg != Reg) {
|
|
|
|
FirstRegSaved = Reg;
|
|
|
|
FirstRegSavedTo = Mips::T0;
|
|
|
|
copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
|
|
|
|
}
|
2013-02-08 03:57:41 +00:00
|
|
|
}
|
|
|
|
else
|
2013-08-04 01:13:25 +00:00
|
|
|
Available.reset(Reg);
|
2013-11-24 06:18:50 +00:00
|
|
|
BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
|
2013-08-04 01:13:25 +00:00
|
|
|
NewImm = 0;
|
2013-02-08 03:57:41 +00:00
|
|
|
if (FrameReg == Mips::SP) {
|
2013-08-04 01:13:25 +00:00
|
|
|
SpReg = Available.find_first();
|
|
|
|
if (SpReg == -1) {
|
|
|
|
SpReg = Candidates.find_first();
|
|
|
|
// Candidates.reset(SpReg); // not really needed
|
|
|
|
if (DefReg!= SpReg) {
|
|
|
|
SecondRegSaved = SpReg;
|
2013-02-08 03:57:41 +00:00
|
|
|
SecondRegSavedTo = Mips::T1;
|
|
|
|
}
|
2013-08-04 01:13:25 +00:00
|
|
|
if (SecondRegSaved)
|
|
|
|
copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
|
2013-02-08 03:57:41 +00:00
|
|
|
}
|
2013-08-04 01:13:25 +00:00
|
|
|
else
|
|
|
|
Available.reset(SpReg);
|
2013-02-08 03:57:41 +00:00
|
|
|
copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
|
2013-08-04 01:13:25 +00:00
|
|
|
BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
|
2013-02-08 03:57:41 +00:00
|
|
|
.addReg(Reg);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
|
|
|
|
.addReg(Reg, RegState::Kill);
|
|
|
|
if (FirstRegSaved || SecondRegSaved) {
|
2014-03-02 12:27:27 +00:00
|
|
|
II = std::next(II);
|
2013-02-08 03:57:41 +00:00
|
|
|
if (FirstRegSaved)
|
|
|
|
copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
|
|
|
|
if (SecondRegSaved)
|
|
|
|
copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
|
|
|
|
}
|
|
|
|
return Reg;
|
2012-10-31 05:21:10 +00:00
|
|
|
}
|
|
|
|
|
2013-05-13 17:43:19 +00:00
|
|
|
unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
|
2012-10-17 22:29:54 +00:00
|
|
|
return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
|
2013-11-12 02:27:12 +00:00
|
|
|
Opc == Mips::Bimm16 ||
|
2013-11-15 02:21:52 +00:00
|
|
|
Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
|
|
|
|
Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
|
2012-10-17 22:29:54 +00:00
|
|
|
Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
|
|
|
|
Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
|
|
|
|
Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
|
|
|
|
Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
|
|
|
|
Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
|
|
|
|
Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
|
|
|
|
Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
|
|
|
|
Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
|
2012-07-31 21:49:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I,
|
|
|
|
unsigned Opc) const {
|
|
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
|
|
|
|
}
|
2012-08-02 18:21:47 +00:00
|
|
|
|
2013-02-16 09:47:57 +00:00
|
|
|
const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
|
2013-02-13 20:28:27 +00:00
|
|
|
if (validSpImm8(Imm))
|
2013-02-16 09:47:57 +00:00
|
|
|
return get(Mips::AddiuSpImm16);
|
2013-02-13 20:28:27 +00:00
|
|
|
else
|
2013-02-16 09:47:57 +00:00
|
|
|
return get(Mips::AddiuSpImmX16);
|
2013-02-13 20:28:27 +00:00
|
|
|
}
|
|
|
|
|
2013-02-16 19:04:29 +00:00
|
|
|
void Mips16InstrInfo::BuildAddiuSpImm
|
|
|
|
(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
|
|
|
|
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
|
|
|
|
BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
|
|
|
|
}
|
|
|
|
|
2014-07-18 23:25:00 +00:00
|
|
|
const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) {
|
|
|
|
return new Mips16InstrInfo(STI);
|
2012-08-02 18:21:47 +00:00
|
|
|
}
|
2013-08-04 01:13:25 +00:00
|
|
|
|
|
|
|
bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
|
|
|
|
int64_t Amount) {
|
|
|
|
switch (Opcode) {
|
|
|
|
case Mips::LbRxRyOffMemX16:
|
|
|
|
case Mips::LbuRxRyOffMemX16:
|
|
|
|
case Mips::LhRxRyOffMemX16:
|
|
|
|
case Mips::LhuRxRyOffMemX16:
|
|
|
|
case Mips::SbRxRyOffMemX16:
|
|
|
|
case Mips::ShRxRyOffMemX16:
|
|
|
|
case Mips::LwRxRyOffMemX16:
|
|
|
|
case Mips::SwRxRyOffMemX16:
|
|
|
|
case Mips::SwRxSpImmX16:
|
|
|
|
case Mips::LwRxSpImmX16:
|
|
|
|
return isInt<16>(Amount);
|
|
|
|
case Mips::AddiuRxRyOffMemX16:
|
|
|
|
if ((Reg == Mips::PC) || (Reg == Mips::SP))
|
|
|
|
return isInt<16>(Amount);
|
|
|
|
return isInt<15>(Amount);
|
|
|
|
}
|
|
|
|
llvm_unreachable("unexpected Opcode in validImmediate");
|
|
|
|
}
|
2013-11-13 04:37:52 +00:00
|
|
|
|
|
|
|
/// Measure the specified inline asm to determine an approximation of its
|
|
|
|
/// length.
|
|
|
|
/// Comments (which run till the next SeparatorString or newline) do not
|
|
|
|
/// count as an instruction.
|
|
|
|
/// Any other non-whitespace text is considered an instruction, with
|
|
|
|
/// multiple instructions separated by SeparatorString or newlines.
|
|
|
|
/// Variable-length instructions are not handled here; this function
|
|
|
|
/// may be overloaded in the target code to do that.
|
|
|
|
/// We implement the special case of the .space directive taking only an
|
|
|
|
/// integer argument, which is the size in bytes. This is used for creating
|
|
|
|
/// inline code spacing for testing purposes using inline assembly.
|
|
|
|
///
|
|
|
|
unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
|
|
|
|
const MCAsmInfo &MAI) const {
|
|
|
|
|
|
|
|
// Count the number of instructions in the asm.
|
|
|
|
bool atInsnStart = true;
|
|
|
|
unsigned Length = 0;
|
|
|
|
for (; *Str; ++Str) {
|
|
|
|
if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
|
|
|
|
strlen(MAI.getSeparatorString())) == 0)
|
|
|
|
atInsnStart = true;
|
|
|
|
if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
|
|
|
|
if (strncmp(Str, ".space", 6)==0) {
|
|
|
|
char *EStr; int Sz;
|
|
|
|
Sz = strtol(Str+6, &EStr, 10);
|
|
|
|
while (isspace(*EStr)) ++EStr;
|
|
|
|
if (*EStr=='\0') {
|
|
|
|
DEBUG(dbgs() << "parsed .space " << Sz << '\n');
|
|
|
|
return Sz;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
Length += MAI.getMaxInstLength();
|
|
|
|
atInsnStart = false;
|
|
|
|
}
|
|
|
|
if (atInsnStart && strncmp(Str, MAI.getCommentString(),
|
|
|
|
strlen(MAI.getCommentString())) == 0)
|
|
|
|
atInsnStart = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return Length;
|
|
|
|
}
|