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https://github.com/c64scene-ar/llvm-6502.git
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51 lines
1.8 KiB
TableGen
51 lines
1.8 KiB
TableGen
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//=- HexagonIntrinsicsV3.td - Target Description for Hexagon -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V3 Compiler Intrinsics in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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// MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
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def Hexagon_M2_vrcmpys_s1:
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di_MInst_disi_s1_sat <"vrcmpys", int_hexagon_M2_vrcmpys_s1>;
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def Hexagon_M2_vrcmpys_acc_s1:
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di_MInst_didisi_acc_s1_sat <"vrcmpys", int_hexagon_M2_vrcmpys_acc_s1>;
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def Hexagon_M2_vrcmpys_s1rp:
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si_MInst_disi_s1_rnd_sat <"vrcmpys", int_hexagon_M2_vrcmpys_s1rp>;
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/********************************************************************
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* MTYPE/VB *
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*********************************************************************/
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// MTYPE / VB / Vector reduce add unsigned bytes.
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def Hexagon_M2_vradduh:
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si_MInst_didi <"vradduh", int_hexagon_M2_vradduh>;
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/********************************************************************
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* ALU64/ALU *
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*********************************************************************/
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// ALU64 / ALU / Add.
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def Hexagon_A2_addsp:
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di_ALU64_sidi <"add", int_hexagon_A2_addsp>;
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def Hexagon_A2_addpsat:
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di_ALU64_didi <"add", int_hexagon_A2_addpsat>;
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def Hexagon_A2_maxp:
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di_ALU64_didi <"max", int_hexagon_A2_maxp>;
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def Hexagon_A2_maxup:
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di_ALU64_didi <"maxu", int_hexagon_A2_maxup>;
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