2012-12-11 21:25:42 +00:00
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//=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief AMDGPU specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUSUBTARGET_H
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#define AMDGPUSUBTARGET_H
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#include "AMDILDevice.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "AMDGPUGenSubtargetInfo.inc"
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#define MAX_CB_SIZE (1 << 16)
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namespace llvm {
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class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
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private:
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bool CapsOverride[AMDGPUDeviceInfo::MaxNumberCapabilities];
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const AMDGPUDevice *Device;
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size_t DefaultSize[3];
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std::string DevName;
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bool Is64bit;
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bool Is32on64bit;
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bool DumpCode;
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bool R600ALUInst;
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2013-04-30 00:13:39 +00:00
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bool HasVertexCache;
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2013-05-17 16:49:55 +00:00
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short TexVTXClauseSize;
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2012-12-11 21:25:42 +00:00
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InstrItineraryData InstrItins;
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public:
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AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
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virtual ~AMDGPUSubtarget();
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const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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2013-01-13 16:01:15 +00:00
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virtual void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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2012-12-11 21:25:42 +00:00
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bool isOverride(AMDGPUDeviceInfo::Caps) const;
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bool is64bit() const;
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2013-04-30 00:13:39 +00:00
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bool hasVertexCache() const;
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2013-05-17 16:49:55 +00:00
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short getTexVTXClauseSize() const;
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2012-12-11 21:25:42 +00:00
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// Helper functions to simplify if statements
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bool isTargetELF() const;
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const AMDGPUDevice* device() const;
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std::string getDataLayout() const;
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std::string getDeviceName() const;
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virtual size_t getDefaultSize(uint32_t dim) const;
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bool dumpCode() const { return DumpCode; }
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bool r600ALUEncoding() const { return R600ALUInst; }
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};
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} // End namespace llvm
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#endif // AMDGPUSUBTARGET_H
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