mirror of
https://github.com/c64scene-ar/llvm-6502.git
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207 lines
5.7 KiB
C++
207 lines
5.7 KiB
C++
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//===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "spiller"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include <algorithm>
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#include <map>
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using namespace llvm;
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Spiller::~Spiller() {}
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namespace {
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class TrivialSpiller : public Spiller {
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public:
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TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm) :
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mf(mf), lis(lis), vrm(vrm)
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{
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mfi = mf->getFrameInfo();
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mri = &mf->getRegInfo();
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tii = mf->getTarget().getInstrInfo();
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}
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std::vector<LiveInterval*> spill(LiveInterval *li) {
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DOUT << "Trivial spiller spilling " << *li << "\n";
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assert(li->weight != HUGE_VALF &&
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"Attempting to spill already spilled value.");
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assert(!li->isStackSlot() &&
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"Trying to spill a stack slot.");
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std::vector<LiveInterval*> added;
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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/*unsigned ss = mfi->CreateStackObject(trc->getSize(),
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trc->getAlignment());*/
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unsigned ss = vrm->assignVirt2StackSlot(li->reg);
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MachineRegisterInfo::reg_iterator regItr = mri->reg_begin(li->reg);
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while (regItr != mri->reg_end()) {
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MachineInstr *mi = &*regItr;
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SmallVector<unsigned, 2> indices;
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bool hasUse = false;
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bool hasDef = false;
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for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
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MachineOperand &op = mi->getOperand(i);
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if (!op.isReg() || op.getReg() != li->reg)
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continue;
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hasUse |= mi->getOperand(i).isUse();
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hasDef |= mi->getOperand(i).isDef();
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indices.push_back(i);
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}
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unsigned newVReg = mri->createVirtualRegister(trc);
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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newLI->weight = HUGE_VALF;
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vrm->grow();
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vrm->assignVirt2StackSlot(newVReg, ss);
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for (unsigned i = 0; i < indices.size(); ++i) {
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mi->getOperand(indices[i]).setReg(newVReg);
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if (mi->getOperand(indices[i]).isUse()) {
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mi->getOperand(indices[i]).setIsKill(true);
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}
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}
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if (hasUse) {
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unsigned loadInstIdx = insertLoadFor(mi, ss, newVReg, trc);
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unsigned start = lis->getDefIndex(loadInstIdx),
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end = lis->getUseIndex(lis->getInstructionIndex(mi));
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VNInfo *vni =
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newLI->getNextValue(loadInstIdx, 0, lis->getVNInfoAllocator());
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vni->kills.push_back(lis->getInstructionIndex(mi));
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LiveRange lr(start, end, vni);
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newLI->addRange(lr);
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added.push_back(newLI);
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}
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if (hasDef) {
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unsigned storeInstIdx = insertStoreFor(mi, ss, newVReg, trc);
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unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)),
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end = lis->getUseIndex(storeInstIdx);
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VNInfo *vni =
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newLI->getNextValue(storeInstIdx, 0, lis->getVNInfoAllocator());
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vni->kills.push_back(storeInstIdx);
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LiveRange lr(start, end, vni);
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newLI->addRange(lr);
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added.push_back(newLI);
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}
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regItr = mri->reg_begin(li->reg);
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}
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return added;
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}
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private:
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MachineFunction *mf;
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LiveIntervals *lis;
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MachineFrameInfo *mfi;
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MachineRegisterInfo *mri;
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const TargetInstrInfo *tii;
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VirtRegMap *vrm;
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void makeRoomForInsertBefore(MachineInstr *mi) {
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if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
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lis->computeNumbering();
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}
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assert(lis->hasGapBeforeInstr(lis->getInstructionIndex(mi)));
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}
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unsigned insertStoreFor(MachineInstr *mi, unsigned ss,
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unsigned newVReg,
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const TargetRegisterClass *trc) {
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MachineBasicBlock::iterator nextInstItr(mi);
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++nextInstItr;
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makeRoomForInsertBefore(&*nextInstItr);
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unsigned miIdx = lis->getInstructionIndex(mi);
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tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, newVReg,
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true, ss, trc);
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MachineBasicBlock::iterator storeInstItr(mi);
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++storeInstItr;
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MachineInstr *storeInst = &*storeInstItr;
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unsigned storeInstIdx = miIdx + LiveIntervals::InstrSlots::NUM;
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assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
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"Store inst index already in use.");
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lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
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return storeInstIdx;
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}
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unsigned insertLoadFor(MachineInstr *mi, unsigned ss,
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unsigned newVReg,
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const TargetRegisterClass *trc) {
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MachineBasicBlock::iterator useInstItr(mi);
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makeRoomForInsertBefore(mi);
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unsigned miIdx = lis->getInstructionIndex(mi);
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tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, newVReg, ss, trc);
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MachineBasicBlock::iterator loadInstItr(mi);
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--loadInstItr;
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MachineInstr *loadInst = &*loadInstItr;
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unsigned loadInstIdx = miIdx - LiveIntervals::InstrSlots::NUM;
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assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
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"Load inst index already in use.");
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lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
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return loadInstIdx;
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}
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};
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}
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llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
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VirtRegMap *vrm) {
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return new TrivialSpiller(mf, lis, vrm);
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}
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