2012-02-17 08:55:11 +00:00
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//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//
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2008-02-10 18:45:23 +00:00
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// This file contains the MIPS implementation of the TargetRegisterInfo class.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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#define DEBUG_TYPE "mips-reg-info"
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2012-03-17 18:46:09 +00:00
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#include "MipsRegisterInfo.h"
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2007-06-06 07:42:06 +00:00
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#include "Mips.h"
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2012-01-25 03:55:10 +00:00
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#include "MipsAnalyzeImmediate.h"
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2012-06-14 01:17:36 +00:00
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#include "MipsInstrInfo.h"
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2007-07-11 23:21:31 +00:00
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#include "MipsMachineFunction.h"
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2012-12-03 16:50:05 +00:00
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#include "MipsSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/ValueTypes.h"
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2012-06-28 00:05:13 +00:00
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#include "llvm/DebugInfo.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Type.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2009-07-11 20:10:48 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2009-07-25 00:23:56 +00:00
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#include "llvm/Support/raw_ostream.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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2011-06-27 18:32:37 +00:00
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#define GET_REGINFO_TARGET_DESC
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2011-06-24 01:44:41 +00:00
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#include "MipsGenRegisterInfo.inc"
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2007-06-06 07:42:06 +00:00
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using namespace llvm;
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2012-08-22 23:58:53 +00:00
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MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
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: MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
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2007-06-06 07:42:06 +00:00
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2009-08-12 22:10:57 +00:00
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unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
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2008-07-14 14:42:54 +00:00
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2013-08-20 21:08:22 +00:00
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const TargetRegisterClass *
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MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
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}
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2013-01-22 21:34:25 +00:00
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unsigned
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MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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switch (RC->getID()) {
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default:
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return 0;
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2013-08-06 23:08:38 +00:00
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case Mips::GPR32RegClassID:
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case Mips::GPR64RegClassID:
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2013-08-14 00:53:38 +00:00
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case Mips::DSPRRegClassID: {
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2013-01-22 21:34:25 +00:00
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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return 28 - TFI->hasFP(MF);
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}
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case Mips::FGR32RegClassID:
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return 32;
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case Mips::AFGR64RegClassID:
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return 16;
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case Mips::FGR64RegClassID:
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return 32;
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}
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}
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2011-03-04 17:51:39 +00:00
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// Callee Saved Registers methods
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-08-28 05:13:42 +00:00
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2007-06-06 07:42:06 +00:00
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/// Mips Callee Saved Registers
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2012-03-04 03:33:22 +00:00
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const uint16_t* MipsRegisterInfo::
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2012-06-14 21:10:56 +00:00
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getCalleeSavedRegs(const MachineFunction *MF) const {
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2012-03-01 22:27:29 +00:00
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if (Subtarget.isSingleFloat())
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return CSR_SingleFloatOnly_SaveList;
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2013-08-20 23:38:40 +00:00
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if (Subtarget.isABI_N64())
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return CSR_N64_SaveList;
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if (Subtarget.isABI_N32())
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2012-03-01 22:27:29 +00:00
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return CSR_N32_SaveList;
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2012-03-27 20:35:51 +00:00
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2013-08-20 23:38:40 +00:00
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if (Subtarget.isFP64bit())
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return CSR_O32_FP64_SaveList;
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return CSR_O32_SaveList;
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2012-03-01 22:27:29 +00:00
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}
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2011-09-23 18:11:56 +00:00
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2012-03-01 22:27:29 +00:00
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const uint32_t*
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2012-06-14 21:10:56 +00:00
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MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
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2008-08-06 06:14:43 +00:00
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if (Subtarget.isSingleFloat())
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2012-03-01 22:27:29 +00:00
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return CSR_SingleFloatOnly_RegMask;
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2013-08-20 23:38:40 +00:00
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if (Subtarget.isABI_N64())
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return CSR_N64_RegMask;
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if (Subtarget.isABI_N32())
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2012-03-01 22:27:29 +00:00
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return CSR_N32_RegMask;
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2012-02-28 07:46:26 +00:00
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2013-08-20 23:38:40 +00:00
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if (Subtarget.isFP64bit())
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return CSR_O32_FP64_RegMask;
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return CSR_O32_RegMask;
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2007-06-06 07:42:06 +00:00
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}
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Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
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const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
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return CSR_Mips16RetHelper_RegMask;
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}
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2007-06-06 07:42:06 +00:00
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BitVector MipsRegisterInfo::
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2010-11-18 21:19:35 +00:00
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getReservedRegs(const MachineFunction &MF) const {
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2013-08-06 23:08:38 +00:00
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static const uint16_t ReservedGPR32[] = {
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2012-11-03 00:05:43 +00:00
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Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
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2011-09-23 18:11:56 +00:00
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};
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2013-08-06 23:08:38 +00:00
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static const uint16_t ReservedGPR64[] = {
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2012-11-03 00:05:43 +00:00
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Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
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2011-09-23 18:11:56 +00:00
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};
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2007-06-06 07:42:06 +00:00
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BitVector Reserved(getNumRegs());
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2012-04-20 07:30:17 +00:00
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typedef TargetRegisterClass::const_iterator RegIter;
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2011-09-23 18:11:56 +00:00
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2013-08-06 23:08:38 +00:00
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for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
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Reserved.set(ReservedGPR32[I]);
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2011-09-23 18:11:56 +00:00
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2013-08-06 23:08:38 +00:00
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for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
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Reserved.set(ReservedGPR64[I]);
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2009-03-21 00:05:07 +00:00
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2013-08-20 23:38:40 +00:00
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if (Subtarget.isFP64bit()) {
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2011-09-23 18:11:56 +00:00
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// Reserve all registers in AFGR64.
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2012-04-20 07:30:17 +00:00
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for (RegIter Reg = Mips::AFGR64RegClass.begin(),
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EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
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2011-09-23 18:11:56 +00:00
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Reserved.set(*Reg);
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2012-04-20 07:30:17 +00:00
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} else {
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2012-11-02 23:36:01 +00:00
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// Reserve all registers in FGR64.
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2012-04-20 07:30:17 +00:00
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for (RegIter Reg = Mips::FGR64RegClass.begin(),
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EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
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2011-09-23 18:11:56 +00:00
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Reserved.set(*Reg);
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}
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2012-05-11 01:45:15 +00:00
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// Reserve FP if this function should have a dedicated frame pointer register.
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2012-05-09 01:38:13 +00:00
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if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
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2012-10-28 06:02:37 +00:00
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if (Subtarget.inMips16Mode())
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Reserved.set(Mips::S0);
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else {
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Reserved.set(Mips::FP);
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Reserved.set(Mips::FP_64);
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}
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2012-05-09 01:38:13 +00:00
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}
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2012-03-27 00:40:56 +00:00
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// Reserve hardware registers.
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Reserved.set(Mips::HWR29);
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2012-09-21 23:48:37 +00:00
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// Reserve DSP control register.
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2013-05-03 18:37:49 +00:00
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Reserved.set(Mips::DSPPos);
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Reserved.set(Mips::DSPSCount);
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Reserved.set(Mips::DSPCarry);
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Reserved.set(Mips::DSPEFI);
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Reserved.set(Mips::DSPOutFlag);
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2012-09-21 23:48:37 +00:00
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2013-08-28 10:26:24 +00:00
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// Reserve MSA control registers.
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Reserved.set(Mips::MSAIR);
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Reserved.set(Mips::MSACSR);
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Reserved.set(Mips::MSAAccess);
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Reserved.set(Mips::MSASave);
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Reserved.set(Mips::MSAModify);
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Reserved.set(Mips::MSARequest);
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Reserved.set(Mips::MSAMap);
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Reserved.set(Mips::MSAUnmap);
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2012-07-10 00:19:06 +00:00
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// Reserve RA if in mips16 mode.
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if (Subtarget.inMips16Mode()) {
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Reserved.set(Mips::RA);
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Reserved.set(Mips::RA_64);
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2013-08-04 01:13:25 +00:00
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Reserved.set(Mips::T0);
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Reserved.set(Mips::T1);
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2012-07-10 00:19:06 +00:00
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}
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2012-08-22 03:18:13 +00:00
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// Reserve GP if small section is used.
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if (Subtarget.useSmallSection()) {
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Reserved.set(Mips::GP);
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Reserved.set(Mips::GP_64);
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}
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2007-06-06 07:42:06 +00:00
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return Reserved;
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}
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2012-03-28 00:24:17 +00:00
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bool
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MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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2012-04-23 21:39:35 +00:00
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bool
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MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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return true;
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}
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2007-06-06 07:42:06 +00:00
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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2010-08-26 23:32:16 +00:00
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void MipsRegisterInfo::
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2009-10-07 17:12:56 +00:00
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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2013-01-31 20:02:54 +00:00
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unsigned FIOperandNum, RegScavenger *RS) const {
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2007-11-05 03:02:32 +00:00
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MachineInstr &MI = *II;
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2007-06-06 07:42:06 +00:00
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MachineFunction &MF = *MI.getParent()->getParent();
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2012-08-22 06:07:19 +00:00
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DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
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2009-08-23 06:49:22 +00:00
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errs() << "<--------->\n" << MI);
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2008-08-02 19:42:36 +00:00
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2013-01-31 20:02:54 +00:00
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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2012-01-25 03:55:10 +00:00
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uint64_t stackSize = MF.getFrameInfo()->getStackSize();
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int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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2007-06-06 07:42:06 +00:00
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2009-08-23 06:49:22 +00:00
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DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
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<< "spOffset : " << spOffset << "\n"
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<< "stackSize : " << stackSize << "\n");
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2007-06-06 07:42:06 +00:00
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2013-01-31 20:02:54 +00:00
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eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
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2007-06-06 07:42:06 +00:00
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}
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unsigned MipsRegisterInfo::
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2009-11-12 20:49:22 +00:00
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getFrameRegister(const MachineFunction &MF) const {
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2011-01-10 12:39:04 +00:00
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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2011-11-15 18:53:55 +00:00
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bool IsN64 = Subtarget.isABI_N64();
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2010-11-18 21:19:35 +00:00
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2012-10-28 06:02:37 +00:00
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if (Subtarget.inMips16Mode())
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return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
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else
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return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
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(IsN64 ? Mips::SP_64 : Mips::SP);
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2007-06-06 07:42:06 +00:00
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}
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