6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-17 03:30:28 +00:00
Code Issues Projects Releases Wiki Activity
8b580ccba0
llvm-6502/test/MC/AArch64/neon-mla-mls-instructions.s

63 lines
2.9 KiB
ArmAsm
Raw Normal View History

AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:20:35 +00:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207119 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 15:04:20 +00:00
// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:20:35 +00:00
// Check that the assembler can handle the documented syntax for AArch64
//----------------------------------------------------------------------
// Vector Integer Multiply-accumulate
//----------------------------------------------------------------------
mla v0.8b, v1.8b, v2.8b
mla v0.16b, v1.16b, v2.16b
mla v0.4h, v1.4h, v2.4h
mla v0.8h, v1.8h, v2.8h
mla v0.2s, v1.2s, v2.2s
mla v0.4s, v1.4s, v2.4s
// CHECK: mla v0.8b, v1.8b, v2.8b // encoding: [0x20,0x94,0x22,0x0e]
// CHECK: mla v0.16b, v1.16b, v2.16b // encoding: [0x20,0x94,0x22,0x4e]
// CHECK: mla v0.4h, v1.4h, v2.4h // encoding: [0x20,0x94,0x62,0x0e]
// CHECK: mla v0.8h, v1.8h, v2.8h // encoding: [0x20,0x94,0x62,0x4e]
// CHECK: mla v0.2s, v1.2s, v2.2s // encoding: [0x20,0x94,0xa2,0x0e]
// CHECK: mla v0.4s, v1.4s, v2.4s // encoding: [0x20,0x94,0xa2,0x4e]
//----------------------------------------------------------------------
// Vector Integer Multiply-subtract
//----------------------------------------------------------------------
mls v0.8b, v1.8b, v2.8b
mls v0.16b, v1.16b, v2.16b
mls v0.4h, v1.4h, v2.4h
mls v0.8h, v1.8h, v2.8h
mls v0.2s, v1.2s, v2.2s
mls v0.4s, v1.4s, v2.4s
// CHECK: mls v0.8b, v1.8b, v2.8b // encoding: [0x20,0x94,0x22,0x2e]
// CHECK: mls v0.16b, v1.16b, v2.16b // encoding: [0x20,0x94,0x22,0x6e]
// CHECK: mls v0.4h, v1.4h, v2.4h // encoding: [0x20,0x94,0x62,0x2e]
// CHECK: mls v0.8h, v1.8h, v2.8h // encoding: [0x20,0x94,0x62,0x6e]
// CHECK: mls v0.2s, v1.2s, v2.2s // encoding: [0x20,0x94,0xa2,0x2e]
// CHECK: mls v0.4s, v1.4s, v2.4s // encoding: [0x20,0x94,0xa2,0x6e]
//----------------------------------------------------------------------
// Vector Floating-Point Multiply-accumulate
//----------------------------------------------------------------------
fmla v0.2s, v1.2s, v2.2s
fmla v0.4s, v1.4s, v2.4s
fmla v0.2d, v1.2d, v2.2d
// CHECK: fmla v0.2s, v1.2s, v2.2s // encoding: [0x20,0xcc,0x22,0x0e]
// CHECK: fmla v0.4s, v1.4s, v2.4s // encoding: [0x20,0xcc,0x22,0x4e]
// CHECK: fmla v0.2d, v1.2d, v2.2d // encoding: [0x20,0xcc,0x62,0x4e]
//----------------------------------------------------------------------
// Vector Floating-Point Multiply-subtract
//----------------------------------------------------------------------
fmls v0.2s, v1.2s, v2.2s
fmls v0.4s, v1.4s, v2.4s
fmls v0.2d, v1.2d, v2.2d
// CHECK: fmls v0.2s, v1.2s, v2.2s // encoding: [0x20,0xcc,0xa2,0x0e]
// CHECK: fmls v0.4s, v1.4s, v2.4s // encoding: [0x20,0xcc,0xa2,0x4e]
// CHECK: fmls v0.2d, v1.2d, v2.2d // encoding: [0x20,0xcc,0xe2,0x4e]
Reference in New Issue Copy Permalink