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https://github.com/c64scene-ar/llvm-6502.git
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63 lines
2.3 KiB
LLVM
63 lines
2.3 KiB
LLVM
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -verify-machineinstrs < %s | FileCheck %s
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; An optimization in DAG Combiner to fold
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; (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...))
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; will generate nodes like:
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; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
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; And such nodes will be defaultly scalarized in type legalization. But such
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; scalarization will cause an assertion failure, as v1i64 is a legal type in
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; AArch64. We change the default behaviour from be scalarized to be widen.
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; FIXME: Currently XTN is generated for v1i32, but it can be optimized.
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; Just like v1i16 and v1i8, there is no XTN generated.
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define <2 x i32> @test_v1i32_0(<1 x i64> %in0) {
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; CHECK-LABEL: test_v1i32_0:
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; CHECK: xtn v0.2s, v0.2d
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%1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <2 x i32> <i32 0, i32 undef>
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%2 = trunc <2 x i64> %1 to <2 x i32>
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ret <2 x i32> %2
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}
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define <2 x i32> @test_v1i32_1(<1 x i64> %in0) {
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; CHECK-LABEL: test_v1i32_1:
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; CHECK: xtn v0.2s, v0.2d
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; CHECK-NEXT: dup v0.2s, v0.s[0]
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%1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <2 x i32> <i32 undef, i32 0>
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%2 = trunc <2 x i64> %1 to <2 x i32>
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ret <2 x i32> %2
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}
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define <4 x i16> @test_v1i16_0(<1 x i64> %in0) {
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; CHECK-LABEL: test_v1i16_0:
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; CHECK-NOT: xtn
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%1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%2 = trunc <4 x i64> %1 to <4 x i16>
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ret <4 x i16> %2
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}
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define <4 x i16> @test_v1i16_1(<1 x i64> %in0) {
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; CHECK-LABEL: test_v1i16_1:
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; CHECK-NOT: xtn
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; CHECK: dup v0.4h, v0.h[0]
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%1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 undef>
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%2 = trunc <4 x i64> %1 to <4 x i16>
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ret <4 x i16> %2
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}
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define <8 x i8> @test_v1i8_0(<1 x i64> %in0) {
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; CHECK-LABEL: test_v1i8_0:
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; CHECK-NOT: xtn
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%1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%2 = trunc <8 x i64> %1 to <8 x i8>
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ret <8 x i8> %2
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}
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define <8 x i8> @test_v1i8_1(<1 x i64> %in0) {
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; CHECK-LABEL: test_v1i8_1:
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; CHECK-NOT: xtn
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; CHECK: dup v0.8b, v0.b[0]
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%1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <8 x i32> <i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%2 = trunc <8 x i64> %1 to <8 x i8>
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ret <8 x i8> %2
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}
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