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https://github.com/c64scene-ar/llvm-6502.git
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59 lines
1.9 KiB
LLVM
59 lines
1.9 KiB
LLVM
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone
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declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
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declare float @llvm.sqrt.f32(float) nounwind readnone
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declare double @llvm.sqrt.f64(double) nounwind readnone
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; FUNC-LABEL: @rcp_f32
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; SI: V_RCP_F32_e32
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define void @rcp_f32(float addrspace(1)* %out, float %src) nounwind {
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%rcp = call float @llvm.AMDGPU.rcp.f32(float %src) nounwind readnone
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @rcp_f64
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; SI: V_RCP_F64_e32
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define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind {
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%rcp = call double @llvm.AMDGPU.rcp.f64(double %src) nounwind readnone
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @rcp_pat_f32
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; SI: V_RCP_F32_e32
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define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
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%rcp = fdiv float 1.0, %src
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @rcp_pat_f64
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; SI: V_RCP_F64_e32
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define void @rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind {
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%rcp = fdiv double 1.0, %src
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @rsq_rcp_pat_f32
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; SI: V_RSQ_F32_e32
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define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
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%sqrt = call float @llvm.sqrt.f32(float %src) nounwind readnone
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%rcp = call float @llvm.AMDGPU.rcp.f32(float %sqrt) nounwind readnone
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @rsq_rcp_pat_f64
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; SI: V_RSQ_F64_e32
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define void @rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind {
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%sqrt = call double @llvm.sqrt.f64(double %src) nounwind readnone
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%rcp = call double @llvm.AMDGPU.rcp.f64(double %sqrt) nounwind readnone
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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