llvm-6502/test/CodeGen/X86/cmpxchg16b.ll

; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s

; Basic 128-bit cmpxchg
define void @t1(i128* nocapture %p) nounwind ssp {
entry:
; CHECK: movl	$1, %ebx
; CHECK: lock
; CHECK-NEXT: cmpxchg16b
  %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst
  ret void
}

; FIXME: Handle 128-bit atomicrmw/load atomic/store atomic
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-26 21:21:21 +00:00			`; RUN: llc < %s -march=x86-64 -mcpu=core2 \| FileCheck %s`

			`; Basic 128-bit cmpxchg`
			`define void @t1(i128* nocapture %p) nounwind ssp {`
			`entry:`
FileCheck hygiene. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147580 91177308-0d34-0410-b5e6-96231b3b80d8 2012-01-05 00:43:34 +00:00			`; CHECK: movl $1, %ebx`
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-26 21:21:21 +00:00			`; CHECK: lock`
			`; CHECK-NEXT: cmpxchg16b`
			`%r = cmpxchg i128* %p, i128 0, i128 1 seq_cst`
			`ret void`
			`}`

			`; FIXME: Handle 128-bit atomicrmw/load atomic/store atomic`