llvm-6502/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll

; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
; RUN: llc -march=mipsel < %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s

; This test originally failed to select code for a truncstore of a
; build_vector.
; It should at least successfully build.

define void @autogen_SD742806235(i8*, i32*, i64*, i32, i64, i8) {
BB:
  %A4 = alloca double
  %A3 = alloca double
  %A2 = alloca <8 x i8>
  %A1 = alloca <4 x float>
  %A = alloca i1
  store i8 %5, i8* %0
  store i8 %5, i8* %0
  store i8 %5, i8* %0
  store <8 x i8> <i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1>, <8 x i8>* %A2
  store i8 %5, i8* %0
  ret void
}
[mips][msa] Expand all truncstores and loadexts for MSA as well as DSP git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8 2013-09-27 09:44:59 +00:00			`; RUN: llc -march=mips < %s`
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8 2013-09-27 10:08:31 +00:00			`; RUN: llc -march=mips -mattr=+msa,+fp64 < %s`
[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws \| (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8 2013-11-15 11:04:16 +00:00			`; RUN: llc -march=mipsel < %s`
			`; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s`
[mips][msa] Expand all truncstores and loadexts for MSA as well as DSP git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8 2013-09-27 09:44:59 +00:00
			`; This test originally failed to select code for a truncstore of a`
			`; build_vector.`
			`; It should at least successfully build.`

			`define void @autogen_SD742806235(i8, i32, i64*, i32, i64, i8) {`
			`BB:`
			`%A4 = alloca double`
			`%A3 = alloca double`
			`%A2 = alloca <8 x i8>`
			`%A1 = alloca <4 x float>`
			`%A = alloca i1`
			`store i8 %5, i8* %0`
			`store i8 %5, i8* %0`
			`store i8 %5, i8* %0`
			`store <8 x i8> <i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1>, <8 x i8>* %A2`
			`store i8 %5, i8* %0`
			`ret void`
			`}`