Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
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@ This test has a partner (ldr-pseudo.s) that contains matching
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@ tests for the ldr-pseudo on linux targets. We need separate files
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@ because the syntax for switching sections and temporary labels differs
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@ between darwin and linux. Any tests added here should have a matching
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@ test added there.
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@RUN: llvm-mc -triple armv7-apple-darwin %s | FileCheck %s
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@RUN: llvm-mc -triple thumbv5-apple-darwin %s | FileCheck %s
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@RUN: llvm-mc -triple thumbv7-apple-darwin %s | FileCheck %s
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@
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@ Check that large constants are converted to ldr from constant pool
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@
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@ simple test
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.section __TEXT,b,regular,pure_instructions
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@ CHECK-LABEL: f3:
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f3:
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ldr r0, =0x10001
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@ CHECK: ldr r0, Ltmp0
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@ loading multiple constants
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.section __TEXT,c,regular,pure_instructions
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@ CHECK-LABEL: f4:
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f4:
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ldr r0, =0x10002
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@ CHECK: ldr r0, Ltmp1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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ldr r0, =0x10003
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@ CHECK: ldr r0, Ltmp2
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adds r0, r0, #1
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adds r0, r0, #1
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@ TODO: the same constants should have the same constant pool location
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.section __TEXT,d,regular,pure_instructions
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@ CHECK-LABEL: f5:
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f5:
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ldr r0, =0x10004
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@ CHECK: ldr r0, Ltmp3
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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ldr r0, =0x10004
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@ CHECK: ldr r0, Ltmp4
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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@ a section defined in multiple pieces should be merged and use a single constant pool
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.section __TEXT,e,regular,pure_instructions
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@ CHECK-LABEL: f6:
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f6:
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ldr r0, =0x10006
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@ CHECK: ldr r0, Ltmp5
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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.section __TEXT,f,regular,pure_instructions
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@ CHECK-LABEL: f7:
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f7:
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adds r0, r0, #1
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adds r0, r0, #1
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adds r0, r0, #1
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.section __TEXT,e,regular,pure_instructions
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@ CHECK-LABEL: f8:
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f8:
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adds r0, r0, #1
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ldr r0, =0x10007
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@ CHECK: ldr r0, Ltmp6
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adds r0, r0, #1
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adds r0, r0, #1
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@
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@ Check that symbols can be loaded using ldr pseudo
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@
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@ load an undefined symbol
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.section __TEXT,g,regular,pure_instructions
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@ CHECK-LABEL: f9:
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f9:
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ldr r0, =foo
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@ CHECK: ldr r0, Ltmp7
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@ load a symbol from another section
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.section __TEXT,h,regular,pure_instructions
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@ CHECK-LABEL: f10:
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f10:
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ldr r0, =f5
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@ CHECK: ldr r0, Ltmp8
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@ load a symbol from the same section
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.section __TEXT,i,regular,pure_instructions
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@ CHECK-LABEL: f11:
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f11:
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ldr r0, =f12
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@ CHECK: ldr r0, Ltmp9
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@ CHECK-LABEL: f12:
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f12:
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adds r0, r0, #1
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adds r0, r0, #1
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|
.section __TEXT,j,regular,pure_instructions
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@ mix of symbols and constants
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@ CHECK-LABEL: f13:
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f13:
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adds r0, r0, #1
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adds r0, r0, #1
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ldr r0, =0x101
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@ CHECK: ldr r0, Ltmp10
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|
adds r0, r0, #1
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|
adds r0, r0, #1
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|
|
ldr r0, =bar
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|
@ CHECK: ldr r0, Ltmp11
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|
adds r0, r0, #1
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|
adds r0, r0, #1
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@
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@ Check for correct usage in other contexts
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@
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@ usage in macro
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.macro useit_in_a_macro
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ldr r0, =0x10008
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ldr r0, =baz
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.endm
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|
.section __TEXT,k,regular,pure_instructions
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@ CHECK-LABEL: f14:
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f14:
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|
useit_in_a_macro
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@ CHECK: ldr r0, Ltmp12
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@ CHECK: ldr r0, Ltmp13
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@ usage with expressions
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|
.section __TEXT,l,regular,pure_instructions
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@ CHECK-LABEL: f15:
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f15:
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|
|
ldr r0, =0x10001+8
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|
|
@ CHECK: ldr r0, Ltmp14
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|
adds r0, r0, #1
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|
ldr r0, =bar+4
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|
@ CHECK: ldr r0, Ltmp15
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|
adds r0, r0, #1
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@
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|
@ Constant Pools
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@
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|
@ CHECK: .section __TEXT,b,regular,pure_instructions
|
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|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp0:
|
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|
|
|
@ CHECK: .long 65537
|
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|
|
@ CHECK: .end_data_region
|
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|
|
|
|
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|
|
@ CHECK: .section __TEXT,c,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp1:
|
|
|
|
|
@ CHECK: .long 65538
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp2:
|
|
|
|
|
@ CHECK: .long 65539
|
|
|
|
|
@ CHECK: .end_data_region
|
|
|
|
|
|
|
|
|
|
@ CHECK: .section __TEXT,d,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp3:
|
|
|
|
|
@ CHECK: .long 65540
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp4:
|
|
|
|
|
@ CHECK: .long 65540
|
|
|
|
|
@ CHECK: .end_data_region
|
|
|
|
|
|
|
|
|
|
@ CHECK: .section __TEXT,e,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp5:
|
|
|
|
|
@ CHECK: .long 65542
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp6:
|
|
|
|
|
@ CHECK: .long 65543
|
|
|
|
|
@ CHECK: .end_data_region
|
|
|
|
|
|
|
|
|
|
@ Should not switch to section because it has no constant pool
|
|
|
|
|
@ CHECK-NOT: .section __TEXT,f,regular,pure_instructions
|
|
|
|
|
|
|
|
|
|
@ CHECK: .section __TEXT,g,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp7:
|
|
|
|
|
@ CHECK: .long foo
|
|
|
|
|
@ CHECK: .end_data_region
|
|
|
|
|
|
|
|
|
|
@ CHECK: .section __TEXT,h,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp8:
|
|
|
|
|
@ CHECK: .long f5
|
|
|
|
|
@ CHECK: .end_data_region
|
|
|
|
|
|
|
|
|
|
@ CHECK: .section __TEXT,i,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp9:
|
|
|
|
|
@ CHECK: .long f12
|
|
|
|
|
@ CHECK: .end_data_region
|
|
|
|
|
|
|
|
|
|
@ CHECK: .section __TEXT,j,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp10:
|
|
|
|
|
@ CHECK: .long 257
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp11:
|
|
|
|
|
@ CHECK: .long bar
|
|
|
|
|
@ CHECK: .end_data_region
|
|
|
|
|
|
|
|
|
|
@ CHECK: .section __TEXT,k,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp12:
|
|
|
|
|
@ CHECK: .long 65544
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp13:
|
|
|
|
|
@ CHECK: .long baz
|
|
|
|
|
@ CHECK: .end_data_region
|
|
|
|
|
|
|
|
|
|
@ CHECK: .section __TEXT,l,regular,pure_instructions
|
|
|
|
|
@ CHECK: .data_region
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp14:
|
|
|
|
|
@ CHECK: .long 65545
|
2014-07-18 16:05:14 +00:00
|
|
|
@ CHECK: .align 2
|
Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,
ldr r0, =0x10001
ldr r1, =bar
will generate this output in the final assembly
ldr r0, .Ltmp0
ldr r1, .Ltmp1
...
.Ltmp0: .long 0x10001
.Ltmp1: .long bar
Sketch of the LDR pseudo implementation:
Keep a map from Section => ConstantPool
When parsing ldr r0, =val
parse val as an MCExpr
get ConstantPool for current Section
Label = CreateTempSymbol()
remember val in ConstantPool at next free slot
add operand to ldr that is MCSymbolRef of Label
On finishParse() callback
Write out all non-empty constant pools
for each Entry in ConstantPool
Emit Entry.Label
Emit Entry.Value
Possible improvements to be added in a later patch:
1. Does not convert load of small constants to mov
(e.g. ldr r0, =0x1 => mov r0, 0x1)
2. Does reuse constant pool entries for same constant
The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 18:12:36 +00:00
|
|
|
@ CHECK-LABEL: Ltmp15:
|
|
|
|
|
@ CHECK: .long bar+4
|
|
|
|
|
@ CHECK: .end_data_region
|