llvm-6502/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt

# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 | FileCheck %s

# CHECK: msr    primask, r0
0x80 0xf3 0x10 0x80

# CHECK: mrs    r0, primask
0xef 0xf3 0x10 0x80
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a slightly different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8 2011-09-28 14:21:38 +00:00			`# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 \| FileCheck %s`

			`# CHECK: msr primask, r0`
			`0x80 0xf3 0x10 0x80`

			`# CHECK: mrs r0, primask`
			`0xef 0xf3 0x10 0x80`