llvm-6502/test/CodeGen/PowerPC/cttz.ll

; Make sure this testcase does not use ctpop
; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s

declare i32 @llvm.cttz.i32(i32, i1)

define i32 @bar(i32 %x) {
entry:
; CHECK: @bar
; CHECK: cntlz
        %tmp.1 = call i32 @llvm.cttz.i32( i32 %x, i1 true )              ; <i32> [#uses=1]
        ret i32 %tmp.1
}
Add testcase for legalizing ISD::CTTZ efficiently. On PPC, ctlz(int) is now codegen'd as this: addi r2, r3, -1 andc r2, r2, r3 cntlzw r2, r2 subfic r3, r2, 32 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21881 91177308-0d34-0410-b5e6-96231b3b80d8 2005-05-11 23:45:54 +00:00			`; Make sure this testcase does not use ctpop`
Fix PowerPC/cttz.ll to specify a cpu (and use FileCheck) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178472 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-01 16:31:56 +00:00			`; RUN: llc < %s -march=ppc32 -mcpu=g5 \| FileCheck %s`
Add testcase for legalizing ISD::CTTZ efficiently. On PPC, ctlz(int) is now codegen'd as this: addi r2, r3, -1 andc r2, r2, r3 cntlzw r2, r2 subfic r3, r2, 32 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21881 91177308-0d34-0410-b5e6-96231b3b80d8 2005-05-11 23:45:54 +00:00
Manually upgrade the test suite to specify the flag to cttz and ctlz. I followed three heuristics for deciding whether to set 'true' or 'false': - Everything target independent got 'true' as that is the expected common output of the GCC builtins. - If the target arch only has one way of implementing this operation, set the flag in the way that exercises the most of codegen. For most architectures this is also the likely path from a GCC builtin, with 'true' being set. It will (eventually) require lowering away that difference, and then lowering to the architecture's operation. - Otherwise, set the flag differently dependending on which target operation should be tested. Let me know if anyone has any issue with this pattern or would like specific tests of another form. This should allow the x86 codegen to just iteratively improve as I teach the backend how to differentiate between the two forms, and everything else should remain exactly the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146370 91177308-0d34-0410-b5e6-96231b3b80d8 2011-12-12 11:59:10 +00:00			`declare i32 @llvm.cttz.i32(i32, i1)`
Add testcase for legalizing ISD::CTTZ efficiently. On PPC, ctlz(int) is now codegen'd as this: addi r2, r3, -1 andc r2, r2, r3 cntlzw r2, r2 subfic r3, r2, 32 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21881 91177308-0d34-0410-b5e6-96231b3b80d8 2005-05-11 23:45:54 +00:00
Remove llvm-upgrade and update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47325 91177308-0d34-0410-b5e6-96231b3b80d8 2008-02-19 08:07:33 +00:00			`define i32 @bar(i32 %x) {`
Add testcase for legalizing ISD::CTTZ efficiently. On PPC, ctlz(int) is now codegen'd as this: addi r2, r3, -1 andc r2, r2, r3 cntlzw r2, r2 subfic r3, r2, 32 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21881 91177308-0d34-0410-b5e6-96231b3b80d8 2005-05-11 23:45:54 +00:00			`entry:`
Fix PowerPC/cttz.ll to specify a cpu (and use FileCheck) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178472 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-01 16:31:56 +00:00			`; CHECK: @bar`
[PowerPC] Enable printing instructions using aliases TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8 2015-04-23 18:30:38 +00:00			`; CHECK: cntlz`
Manually upgrade the test suite to specify the flag to cttz and ctlz. I followed three heuristics for deciding whether to set 'true' or 'false': - Everything target independent got 'true' as that is the expected common output of the GCC builtins. - If the target arch only has one way of implementing this operation, set the flag in the way that exercises the most of codegen. For most architectures this is also the likely path from a GCC builtin, with 'true' being set. It will (eventually) require lowering away that difference, and then lowering to the architecture's operation. - Otherwise, set the flag differently dependending on which target operation should be tested. Let me know if anyone has any issue with this pattern or would like specific tests of another form. This should allow the x86 codegen to just iteratively improve as I teach the backend how to differentiate between the two forms, and everything else should remain exactly the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146370 91177308-0d34-0410-b5e6-96231b3b80d8 2011-12-12 11:59:10 +00:00			`%tmp.1 = call i32 @llvm.cttz.i32( i32 %x, i1 true ) ; <i32> [#uses=1]`
Remove llvm-upgrade and update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47325 91177308-0d34-0410-b5e6-96231b3b80d8 2008-02-19 08:07:33 +00:00			`ret i32 %tmp.1`
Add testcase for legalizing ISD::CTTZ efficiently. On PPC, ctlz(int) is now codegen'd as this: addi r2, r3, -1 andc r2, r2, r3 cntlzw r2, r2 subfic r3, r2, 32 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21881 91177308-0d34-0410-b5e6-96231b3b80d8 2005-05-11 23:45:54 +00:00			`}`
Remove llvm-upgrade and update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47325 91177308-0d34-0410-b5e6-96231b3b80d8 2008-02-19 08:07:33 +00:00