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llvm-6502/test/CodeGen/X86/pr16031.ll

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Revert "Temporarily enable MI-Sched on X86." This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:48:58 +00:00
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s
X86: Bad peephole interaction between adc, MOV32r0 The peephole tries to reorder MOV32r0 instructions such that they are before the instruction that modifies EFLAGS. The problem is that the peephole does not consider the case where the instruction that modifies EFLAGS also depends on the previous state of EFLAGS. Instead, walk backwards until we find an instruction that has a def for EFLAGS but does not have a use. If we find such an instruction, insert the MOV32r0 before it. If it cannot find such an instruction, skip the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182184 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 01:02:03 +00:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 06:24:09 +00:00
; CHECK-LABEL: main:
X86: Bad peephole interaction between adc, MOV32r0 The peephole tries to reorder MOV32r0 instructions such that they are before the instruction that modifies EFLAGS. The problem is that the peephole does not consider the case where the instruction that modifies EFLAGS also depends on the previous state of EFLAGS. Instead, walk backwards until we find an instruction that has a def for EFLAGS but does not have a use. If we find such an instruction, insert the MOV32r0 before it. If it cannot find such an instruction, skip the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182184 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 01:02:03 +00:00
; CHECK: pushl %esi
; CHECK-NEXT: movl $-12, %eax
; CHECK-NEXT: movl $-1, %edx
; CHECK-NEXT: testb $1, 8(%esp)
; CHECK-NEXT: cmovel %edx, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: addl $-1, %esi
; CHECK-NEXT: movl $-1, %esi
; CHECK-NEXT: adcl $-1, %esi
; CHECK-NEXT: cmovsl %ecx, %eax
; CHECK-NEXT: cmovsl %ecx, %edx
; CHECK-NEXT: popl %esi
define i64 @main(i1 %tobool1) nounwind {
entry:
%0 = zext i1 %tobool1 to i32
%. = xor i32 %0, 1
%.21 = select i1 %tobool1, i32 -12, i32 -1
%conv = sext i32 %.21 to i64
%1 = add i64 %conv, -1
%cmp10 = icmp slt i64 %1, 0
%sub17 = select i1 %cmp10, i64 0, i64 %conv
ret i64 %sub17
}
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