llvm-6502/test/CodeGen/Mips/mips32r6/compatibility.ll

; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s
; RUN: not llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s

; CHECK: foo:
; DSP: MIPS32r6 is not compatible with the DSP ASE

define void @foo() nounwind {
  ret void
}
[mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 Summary: Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these processors. I've also included comments to describe removed and re-encoded instructions, along with placeholder def's for the new instructions but there are no functional changes to codegen at this point. Reviewers: jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208399 91177308-0d34-0410-b5e6-96231b3b80d8 2014-05-09 09:46:21 +00:00			`; RUN: llc -march=mipsel -mcpu=mips32r6 < %s \| FileCheck %s`
			`; RUN: not llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 \| FileCheck --check-prefix=DSP %s`

			`; CHECK: foo:`
			`; DSP: MIPS32r6 is not compatible with the DSP ASE`

			`define void @foo() nounwind {`
			`ret void`
			`}`