llvm-6502/test/CodeGen/X86/x86_64-mul-by-const.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; Formerly there were two shifts.  rdar://8771012.

define i32 @f9188_mul365384439_shift27(i32 %A) nounwind {
; CHECK:  imulq $365384439,
; CHECK:  shrq  $59, %rax
        %tmp1 = udiv i32 %A, 1577682821         ; <i32> [#uses=1]
        ret i32 %tmp1
}
Add a transform to DAG Combiner. This improves the code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122090 91177308-0d34-0410-b5e6-96231b3b80d8 2010-12-17 21:45:49 +00:00			`; RUN: llc < %s -mtriple=x86_64-apple-darwin \| FileCheck %s`
Cosmetic changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122259 91177308-0d34-0410-b5e6-96231b3b80d8 2010-12-20 20:10:50 +00:00			`; Formerly there were two shifts. rdar://8771012.`
Add a transform to DAG Combiner. This improves the code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122090 91177308-0d34-0410-b5e6-96231b3b80d8 2010-12-17 21:45:49 +00:00
			`define i32 @f9188_mul365384439_shift27(i32 %A) nounwind {`
			`; CHECK: imulq $365384439,`
			`; CHECK: shrq $59, %rax`
			`%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]`
			`ret i32 %tmp1`
			`}`