llvm-6502/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt

# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding}

# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# if m == 15 then UNPREDICTABLE
0x8f 0x60 0xb7 0xe7
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-26 20:43:14 +00:00			`# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 \|& grep {potentially undefined instruction encoding}`
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-11 18:34:12 +00:00
			`# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)`
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-11 18:55:42 +00:00			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-11 18:34:12 +00:00			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 1: 1: 0\| 0: 1: 1: 1\| 1: 0: 1: 1\| 0: 1: 1: 1\| 0: 1: 1: 0\| 0: 0: 0: 0\| 1: 0: 0: 0\| 1: 1: 1: 1\|`
			`# -------------------------------------------------------------------------------------------------`
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-11 18:55:42 +00:00			`#`
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-11 18:34:12 +00:00			`# if m == 15 then UNPREDICTABLE`
			`0x8f 0x60 0xb7 0xe7`