2007-12-08 20:24:38 +00:00
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//===-- LegalizeTypesPromote.cpp - Promotion for LegalizeTypes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-12-08 20:24:38 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements promotion support for LegalizeTypes. Promotion is the
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// act of changing a computation in an invalid type to be a computation in a
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// larger type. For example, implementing i8 arithmetic in an i32 register (as
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// is often needed on powerpc for example).
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//
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//===----------------------------------------------------------------------===//
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#include "LegalizeTypes.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Result Promotion
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//===----------------------------------------------------------------------===//
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/// PromoteResult - This method is called when a result of a node is found to be
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/// in need of promotion to a larger type. At this point, the node may also
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/// have invalid operands or may have other results that need expansion, we just
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/// know that (at least) one result needs promotion.
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void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
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DEBUG(cerr << "Promote node result: "; N->dump(&DAG); cerr << "\n");
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SDOperand Result = SDOperand();
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "PromoteResult #" << ResNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to promote this operator!");
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abort();
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case ISD::UNDEF: Result = PromoteResult_UNDEF(N); break;
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case ISD::Constant: Result = PromoteResult_Constant(N); break;
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case ISD::TRUNCATE: Result = PromoteResult_TRUNCATE(N); break;
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case ISD::SIGN_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND: Result = PromoteResult_INT_EXTEND(N); break;
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case ISD::FP_ROUND: Result = PromoteResult_FP_ROUND(N); break;
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT: Result = PromoteResult_FP_TO_XINT(N); break;
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case ISD::SETCC: Result = PromoteResult_SETCC(N); break;
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case ISD::LOAD: Result = PromoteResult_LOAD(cast<LoadSDNode>(N)); break;
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2008-02-24 07:36:03 +00:00
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case ISD::BUILD_PAIR: Result = PromoteResult_BUILD_PAIR(N); break;
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
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case ISD::BIT_CONVERT: Result = PromoteResult_BIT_CONVERT(N); break;
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2007-12-08 20:24:38 +00:00
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL: Result = PromoteResult_SimpleIntBinOp(N); break;
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case ISD::SDIV:
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case ISD::SREM: Result = PromoteResult_SDIV(N); break;
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case ISD::UDIV:
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case ISD::UREM: Result = PromoteResult_UDIV(N); break;
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case ISD::SHL: Result = PromoteResult_SHL(N); break;
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case ISD::SRA: Result = PromoteResult_SRA(N); break;
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case ISD::SRL: Result = PromoteResult_SRL(N); break;
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case ISD::SELECT: Result = PromoteResult_SELECT(N); break;
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case ISD::SELECT_CC: Result = PromoteResult_SELECT_CC(N); break;
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2008-02-13 18:01:53 +00:00
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case ISD::CTLZ: Result = PromoteResult_CTLZ(N); break;
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case ISD::CTPOP: Result = PromoteResult_CTPOP(N); break;
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case ISD::CTTZ: Result = PromoteResult_CTTZ(N); break;
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
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case ISD::EXTRACT_VECTOR_ELT:
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Result = PromoteResult_EXTRACT_VECTOR_ELT(N);
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break;
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2007-12-08 20:24:38 +00:00
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}
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LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
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2007-12-08 20:24:38 +00:00
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// If Result is null, the sub-method took care of registering the result.
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if (Result.Val)
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SetPromotedOp(SDOperand(N, ResNo), Result);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_UNDEF(SDNode *N) {
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return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) {
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MVT::ValueType VT = N->getValueType(0);
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// Zero extend things like i1, sign extend everything else. It shouldn't
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// matter in theory which one we pick, but this tends to give better code?
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unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
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SDOperand(N, 0));
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assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
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return Result;
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}
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SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) {
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SDOperand Res;
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switch (getTypeAction(N->getOperand(0).getValueType())) {
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default: assert(0 && "Unknown type action!");
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case Legal:
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case Expand:
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Res = N->getOperand(0);
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break;
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case Promote:
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Res = GetPromotedOp(N->getOperand(0));
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break;
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}
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MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) &&
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"Truncation doesn't make sense!");
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if (Res.getValueType() == NVT)
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return Res;
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// Truncate to NVT instead of VT
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return DAG.getNode(ISD::TRUNCATE, NVT, Res);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) {
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MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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if (getTypeAction(N->getOperand(0).getValueType()) == Promote) {
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SDOperand Res = GetPromotedOp(N->getOperand(0));
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assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) &&
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"Extension doesn't make sense!");
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// If the result and operand types are the same after promotion, simplify
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// to an in-register extension.
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if (NVT == Res.getValueType()) {
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// The high bits are not guaranteed to be anything. Insert an extend.
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if (N->getOpcode() == ISD::SIGN_EXTEND)
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
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DAG.getValueType(N->getOperand(0).getValueType()));
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if (N->getOpcode() == ISD::ZERO_EXTEND)
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return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
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assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
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return Res;
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}
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}
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// Otherwise, just extend the original operand all the way to the larger type.
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return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
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// NOTE: Assumes input is legal.
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2008-01-17 07:00:52 +00:00
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if (N->getConstantOperandVal(1) == 0)
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return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
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N->getOperand(0), DAG.getValueType(N->getValueType(0)));
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// If the precision discard isn't needed, just return the operand unrounded.
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return N->getOperand(0);
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2007-12-08 20:24:38 +00:00
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}
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SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
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SDOperand Op = N->getOperand(0);
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// If the operand needed to be promoted, do so now.
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if (getTypeAction(Op.getValueType()) == Promote)
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// The input result is prerounded, so we don't have to do anything special.
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Op = GetPromotedOp(Op);
|
|
|
|
|
|
|
|
unsigned NewOpc = N->getOpcode();
|
|
|
|
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
|
|
|
|
|
|
|
|
// If we're promoting a UINT to a larger size, check to see if the new node
|
|
|
|
// will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
|
|
|
|
// we can use that instead. This allows us to generate better code for
|
|
|
|
// FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
|
|
|
|
// legal, such as PowerPC.
|
|
|
|
if (N->getOpcode() == ISD::FP_TO_UINT) {
|
|
|
|
if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
|
|
|
|
(TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
|
|
|
|
TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
|
|
|
|
NewOpc = ISD::FP_TO_SINT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return DAG.getNode(NewOpc, NVT, Op);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
|
2008-03-10 15:42:14 +00:00
|
|
|
assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
|
2008-03-20 01:22:40 +00:00
|
|
|
&& "SetCC type is not legal??");
|
2008-03-10 15:42:14 +00:00
|
|
|
return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
|
2008-03-20 01:22:40 +00:00
|
|
|
N->getOperand(0), N->getOperand(1), N->getOperand(2));
|
2007-12-08 20:24:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
|
|
|
|
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
|
|
|
|
ISD::LoadExtType ExtType =
|
|
|
|
ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
|
|
|
|
SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
|
|
|
|
N->getSrcValue(), N->getSrcValueOffset(),
|
2008-01-30 00:15:11 +00:00
|
|
|
N->getMemoryVT(), N->isVolatile(),
|
2007-12-08 20:24:38 +00:00
|
|
|
N->getAlignment());
|
|
|
|
|
|
|
|
// Legalized the chain result - switch anything that used the old chain to
|
|
|
|
// use the new one.
|
|
|
|
ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
|
|
|
|
return Res;
|
|
|
|
}
|
|
|
|
|
2008-02-24 07:36:03 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_BUILD_PAIR(SDNode *N) {
|
|
|
|
// The pair element type may be legal, or may not promote to the same type as
|
2008-03-11 06:41:14 +00:00
|
|
|
// the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
|
|
|
|
return DAG.getNode(ISD::ANY_EXTEND,
|
|
|
|
TLI.getTypeToTransformTo(N->getValueType(0)),
|
|
|
|
JoinIntegers(N->getOperand(0), N->getOperand(1)));
|
2008-02-24 07:36:03 +00:00
|
|
|
}
|
|
|
|
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) {
|
|
|
|
SDOperand InOp = N->getOperand(0);
|
|
|
|
MVT::ValueType InVT = InOp.getValueType();
|
|
|
|
MVT::ValueType NInVT = TLI.getTypeToTransformTo(InVT);
|
|
|
|
MVT::ValueType OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
|
|
|
|
|
|
|
|
switch (getTypeAction(InVT)) {
|
|
|
|
default:
|
|
|
|
assert(false && "Unknown type action!");
|
|
|
|
break;
|
|
|
|
case Legal:
|
|
|
|
break;
|
|
|
|
case Promote:
|
|
|
|
if (MVT::getSizeInBits(OutVT) == MVT::getSizeInBits(NInVT))
|
|
|
|
// The input promotes to the same size. Convert the promoted value.
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedOp(InOp));
|
|
|
|
break;
|
|
|
|
case Expand:
|
|
|
|
break;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
case FloatToInt:
|
|
|
|
// Promote the integer operand by hand.
|
|
|
|
return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetIntegerOp(InOp));
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
case Scalarize:
|
|
|
|
// Convert the element to an integer and promote it by hand.
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
return DAG.getNode(ISD::ANY_EXTEND, OutVT,
|
|
|
|
BitConvertToInteger(GetScalarizedOp(InOp)));
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
case Split:
|
|
|
|
// For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
|
|
|
|
// pieces of the input into integers and reassemble in the final type.
|
|
|
|
SDOperand Lo, Hi;
|
|
|
|
GetSplitOp(N->getOperand(0), Lo, Hi);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
Lo = BitConvertToInteger(Lo);
|
|
|
|
Hi = BitConvertToInteger(Hi);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
|
2008-03-11 06:41:14 +00:00
|
|
|
InOp = DAG.getNode(ISD::ANY_EXTEND,
|
|
|
|
MVT::getIntegerType(MVT::getSizeInBits(OutVT)),
|
|
|
|
JoinIntegers(Lo, Hi));
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, lower the bit-convert to a store/load from the stack, then
|
|
|
|
// promote the load.
|
|
|
|
SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
|
|
|
|
return PromoteResult_LOAD(cast<LoadSDNode>(Op.Val));
|
|
|
|
}
|
|
|
|
|
2007-12-08 20:24:38 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
|
|
|
|
// The input may have strange things in the top bits of the registers, but
|
|
|
|
// these operations don't care. They may have weird bits going out, but
|
|
|
|
// that too is okay if they are integer operations.
|
|
|
|
SDOperand LHS = GetPromotedOp(N->getOperand(0));
|
|
|
|
SDOperand RHS = GetPromotedOp(N->getOperand(1));
|
|
|
|
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
|
|
|
|
// Sign extend the input.
|
|
|
|
SDOperand LHS = GetPromotedOp(N->getOperand(0));
|
|
|
|
SDOperand RHS = GetPromotedOp(N->getOperand(1));
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
|
|
|
|
DAG.getValueType(VT));
|
|
|
|
RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
|
|
|
|
DAG.getValueType(VT));
|
|
|
|
|
|
|
|
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
|
|
|
|
// Zero extend the input.
|
|
|
|
SDOperand LHS = GetPromotedOp(N->getOperand(0));
|
|
|
|
SDOperand RHS = GetPromotedOp(N->getOperand(1));
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
LHS = DAG.getZeroExtendInReg(LHS, VT);
|
|
|
|
RHS = DAG.getZeroExtendInReg(RHS, VT);
|
|
|
|
|
|
|
|
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
|
|
|
|
return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
|
|
|
|
GetPromotedOp(N->getOperand(0)), N->getOperand(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) {
|
|
|
|
// The input value must be properly sign extended.
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
|
|
|
|
SDOperand Res = GetPromotedOp(N->getOperand(0));
|
|
|
|
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
|
|
|
|
return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) {
|
|
|
|
// The input value must be properly zero extended.
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
|
|
|
|
SDOperand Res = GetPromotedZExtOp(N->getOperand(0));
|
|
|
|
return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_SELECT(SDNode *N) {
|
|
|
|
SDOperand LHS = GetPromotedOp(N->getOperand(1));
|
|
|
|
SDOperand RHS = GetPromotedOp(N->getOperand(2));
|
|
|
|
return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) {
|
|
|
|
SDOperand LHS = GetPromotedOp(N->getOperand(2));
|
|
|
|
SDOperand RHS = GetPromotedOp(N->getOperand(3));
|
|
|
|
return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
|
|
|
|
N->getOperand(1), LHS, RHS, N->getOperand(4));
|
|
|
|
}
|
|
|
|
|
2008-02-13 18:01:53 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_CTLZ(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
|
|
|
MVT::ValueType OVT = N->getValueType(0);
|
|
|
|
MVT::ValueType NVT = Op.getValueType();
|
|
|
|
// Zero extend to the promoted type and do the count there.
|
|
|
|
Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
|
|
|
|
// Subtract off the extra leading bits in the bigger type.
|
|
|
|
return DAG.getNode(ISD::SUB, NVT, Op,
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(NVT) -
|
|
|
|
MVT::getSizeInBits(OVT), NVT));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_CTPOP(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
|
|
|
MVT::ValueType OVT = N->getValueType(0);
|
|
|
|
MVT::ValueType NVT = Op.getValueType();
|
|
|
|
// Zero extend to the promoted type and do the count there.
|
|
|
|
return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
|
|
|
MVT::ValueType OVT = N->getValueType(0);
|
|
|
|
MVT::ValueType NVT = Op.getValueType();
|
|
|
|
// The count is the same in the promoted type except if the original
|
|
|
|
// value was zero. This can be handled by setting the bit just off
|
|
|
|
// the top of the original type.
|
|
|
|
Op = DAG.getNode(ISD::OR, NVT, Op,
|
|
|
|
// FIXME: Do this using an APINT constant.
|
|
|
|
DAG.getConstant(1UL << MVT::getSizeInBits(OVT), NVT));
|
|
|
|
return DAG.getNode(ISD::CTTZ, NVT, Op);
|
|
|
|
}
|
2007-12-08 20:24:38 +00:00
|
|
|
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) {
|
|
|
|
MVT::ValueType OldVT = N->getValueType(0);
|
|
|
|
SDOperand OldVec = N->getOperand(0);
|
|
|
|
unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType());
|
|
|
|
|
|
|
|
if (OldElts == 1) {
|
|
|
|
assert(!isTypeLegal(OldVec.getValueType()) &&
|
|
|
|
"Legal one-element vector of a type needing promotion!");
|
|
|
|
// It is tempting to follow GetScalarizedOp by a call to GetPromotedOp,
|
|
|
|
// but this would be wrong because the scalarized value may not yet have
|
|
|
|
// been processed.
|
|
|
|
return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
|
|
|
|
GetScalarizedOp(OldVec));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Convert to a vector half as long with an element type of twice the width,
|
|
|
|
// for example <4 x i16> -> <2 x i32>.
|
|
|
|
assert(!(OldElts & 1) && "Odd length vectors not supported!");
|
|
|
|
MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
|
|
|
|
assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
|
|
|
|
|
|
|
|
SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
|
|
|
|
MVT::getVectorType(NewVT, OldElts / 2),
|
|
|
|
OldVec);
|
|
|
|
|
|
|
|
// Extract the element at OldIdx / 2 from the new vector.
|
|
|
|
SDOperand OldIdx = N->getOperand(1);
|
|
|
|
SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
|
|
|
|
DAG.getConstant(1, TLI.getShiftAmountTy()));
|
|
|
|
SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
|
|
|
|
|
|
|
|
// Select the appropriate half of the element: Lo if OldIdx was even,
|
|
|
|
// Hi if it was odd.
|
|
|
|
SDOperand Lo = Elt;
|
|
|
|
SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(OldVT),
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
|
|
|
|
SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
|
|
|
|
DAG.getConstant(1, TLI.getShiftAmountTy()));
|
|
|
|
return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
|
|
|
|
}
|
|
|
|
|
2007-12-08 20:24:38 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Operand Promotion
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// PromoteOperand - This method is called when the specified operand of the
|
|
|
|
/// specified node is found to need promotion. At this point, all of the result
|
|
|
|
/// types of the node are known to be legal, but other operands of the node may
|
|
|
|
/// need promotion or expansion as well as the specified one.
|
|
|
|
bool DAGTypeLegalizer::PromoteOperand(SDNode *N, unsigned OpNo) {
|
|
|
|
DEBUG(cerr << "Promote node operand: "; N->dump(&DAG); cerr << "\n");
|
|
|
|
SDOperand Res;
|
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default:
|
|
|
|
#ifndef NDEBUG
|
|
|
|
cerr << "PromoteOperand Op #" << OpNo << ": ";
|
|
|
|
N->dump(&DAG); cerr << "\n";
|
|
|
|
#endif
|
|
|
|
assert(0 && "Do not know how to promote this operator's operand!");
|
|
|
|
abort();
|
|
|
|
|
|
|
|
case ISD::ANY_EXTEND: Res = PromoteOperand_ANY_EXTEND(N); break;
|
|
|
|
case ISD::ZERO_EXTEND: Res = PromoteOperand_ZERO_EXTEND(N); break;
|
|
|
|
case ISD::SIGN_EXTEND: Res = PromoteOperand_SIGN_EXTEND(N); break;
|
|
|
|
case ISD::TRUNCATE: Res = PromoteOperand_TRUNCATE(N); break;
|
|
|
|
case ISD::FP_EXTEND: Res = PromoteOperand_FP_EXTEND(N); break;
|
|
|
|
case ISD::FP_ROUND: Res = PromoteOperand_FP_ROUND(N); break;
|
|
|
|
case ISD::SINT_TO_FP:
|
|
|
|
case ISD::UINT_TO_FP: Res = PromoteOperand_INT_TO_FP(N); break;
|
2008-02-24 07:36:03 +00:00
|
|
|
case ISD::BUILD_PAIR: Res = PromoteOperand_BUILD_PAIR(N); break;
|
|
|
|
|
2007-12-08 20:24:38 +00:00
|
|
|
case ISD::SELECT: Res = PromoteOperand_SELECT(N, OpNo); break;
|
|
|
|
case ISD::BRCOND: Res = PromoteOperand_BRCOND(N, OpNo); break;
|
|
|
|
case ISD::BR_CC: Res = PromoteOperand_BR_CC(N, OpNo); break;
|
|
|
|
case ISD::SETCC: Res = PromoteOperand_SETCC(N, OpNo); break;
|
|
|
|
|
|
|
|
case ISD::STORE: Res = PromoteOperand_STORE(cast<StoreSDNode>(N),
|
|
|
|
OpNo); break;
|
2008-02-15 19:34:17 +00:00
|
|
|
|
2008-02-24 07:36:03 +00:00
|
|
|
case ISD::BUILD_VECTOR: Res = PromoteOperand_BUILD_VECTOR(N); break;
|
2008-02-27 10:18:23 +00:00
|
|
|
case ISD::INSERT_VECTOR_ELT:
|
|
|
|
Res = PromoteOperand_INSERT_VECTOR_ELT(N, OpNo);
|
|
|
|
break;
|
2008-02-24 07:36:03 +00:00
|
|
|
|
2008-02-15 19:34:17 +00:00
|
|
|
case ISD::RET: Res = PromoteOperand_RET(N, OpNo); break;
|
2008-02-27 08:53:44 +00:00
|
|
|
|
|
|
|
case ISD::MEMBARRIER: Res = PromoteOperand_MEMBARRIER(N); break;
|
2007-12-08 20:24:38 +00:00
|
|
|
}
|
2008-02-15 19:34:17 +00:00
|
|
|
|
2007-12-08 20:24:38 +00:00
|
|
|
// If the result is null, the sub-method took care of registering results etc.
|
|
|
|
if (!Res.Val) return false;
|
|
|
|
// If the result is N, the sub-method updated N in place.
|
|
|
|
if (Res.Val == N) {
|
|
|
|
// Mark N as new and remark N and its operands. This allows us to correctly
|
|
|
|
// revisit N if it needs another step of promotion and allows us to visit
|
|
|
|
// any new operands to N.
|
2008-02-26 11:21:42 +00:00
|
|
|
ReanalyzeNode(N);
|
2007-12-08 20:24:38 +00:00
|
|
|
return true;
|
|
|
|
}
|
2008-02-26 11:21:42 +00:00
|
|
|
|
2007-12-08 20:24:38 +00:00
|
|
|
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
|
|
|
|
"Invalid operand expansion");
|
|
|
|
|
|
|
|
ReplaceValueWith(SDOperand(N, 0), Res);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_ANY_EXTEND(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
|
|
|
return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_ZERO_EXTEND(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
|
|
|
Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
|
|
|
|
return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_SIGN_EXTEND(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
|
|
|
Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
|
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
|
|
|
|
Op, DAG.getValueType(N->getOperand(0).getValueType()));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_TRUNCATE(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
|
|
|
return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_FP_EXTEND(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
|
|
|
return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
|
|
|
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
2008-01-17 07:00:52 +00:00
|
|
|
return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
|
|
|
|
DAG.getIntPtrConstant(0));
|
2007-12-08 20:24:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
|
|
|
|
SDOperand In = GetPromotedOp(N->getOperand(0));
|
|
|
|
MVT::ValueType OpVT = N->getOperand(0).getValueType();
|
|
|
|
if (N->getOpcode() == ISD::UINT_TO_FP)
|
|
|
|
In = DAG.getZeroExtendInReg(In, OpVT);
|
|
|
|
else
|
|
|
|
In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
|
|
|
|
In, DAG.getValueType(OpVT));
|
|
|
|
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
|
|
|
|
}
|
|
|
|
|
2008-02-24 07:36:03 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_PAIR(SDNode *N) {
|
|
|
|
// Since the result type is legal, the operands must promote to it.
|
|
|
|
MVT::ValueType OVT = N->getOperand(0).getValueType();
|
|
|
|
SDOperand Lo = GetPromotedOp(N->getOperand(0));
|
|
|
|
SDOperand Hi = GetPromotedOp(N->getOperand(1));
|
|
|
|
assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
|
|
|
|
|
|
|
|
Lo = DAG.getZeroExtendInReg(Lo, OVT);
|
|
|
|
Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(OVT),
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
|
|
|
|
}
|
|
|
|
|
2007-12-08 20:24:38 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_SELECT(SDNode *N, unsigned OpNo) {
|
|
|
|
assert(OpNo == 0 && "Only know how to promote condition");
|
|
|
|
SDOperand Cond = GetPromotedOp(N->getOperand(0)); // Promote the condition.
|
|
|
|
|
|
|
|
// The top bits of the promoted condition are not necessarily zero, ensure
|
|
|
|
// that the value is properly zero extended.
|
2008-02-25 21:11:39 +00:00
|
|
|
unsigned BitWidth = Cond.getValueSizeInBits();
|
2007-12-08 20:24:38 +00:00
|
|
|
if (!DAG.MaskedValueIsZero(Cond,
|
2008-02-26 11:21:42 +00:00
|
|
|
APInt::getHighBitsSet(BitWidth, BitWidth-1)))
|
2007-12-08 20:24:38 +00:00
|
|
|
Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
|
|
|
|
|
|
|
|
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
|
|
|
|
N->getOperand(2));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_BRCOND(SDNode *N, unsigned OpNo) {
|
|
|
|
assert(OpNo == 1 && "only know how to promote condition");
|
|
|
|
SDOperand Cond = GetPromotedOp(N->getOperand(1)); // Promote the condition.
|
|
|
|
|
|
|
|
// The top bits of the promoted condition are not necessarily zero, ensure
|
|
|
|
// that the value is properly zero extended.
|
2008-02-25 21:11:39 +00:00
|
|
|
unsigned BitWidth = Cond.getValueSizeInBits();
|
2007-12-08 20:24:38 +00:00
|
|
|
if (!DAG.MaskedValueIsZero(Cond,
|
2008-02-26 11:21:42 +00:00
|
|
|
APInt::getHighBitsSet(BitWidth, BitWidth-1)))
|
2007-12-08 20:24:38 +00:00
|
|
|
Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
|
2008-02-26 11:21:42 +00:00
|
|
|
|
2007-12-08 20:24:38 +00:00
|
|
|
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
|
|
|
|
N->getOperand(2));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_BR_CC(SDNode *N, unsigned OpNo) {
|
|
|
|
assert(OpNo == 2 && "Don't know how to promote this operand");
|
|
|
|
|
|
|
|
SDOperand LHS = N->getOperand(2);
|
|
|
|
SDOperand RHS = N->getOperand(3);
|
|
|
|
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
|
|
|
|
|
|
|
|
// The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
|
|
|
|
// legal types.
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
|
|
|
|
N->getOperand(1), LHS, RHS, N->getOperand(4));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_SETCC(SDNode *N, unsigned OpNo) {
|
|
|
|
assert(OpNo == 0 && "Don't know how to promote this operand");
|
|
|
|
|
|
|
|
SDOperand LHS = N->getOperand(0);
|
|
|
|
SDOperand RHS = N->getOperand(1);
|
|
|
|
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
|
|
|
|
|
|
|
|
// The CC (#2) is always legal.
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
|
|
|
|
}
|
|
|
|
|
|
|
|
/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
|
|
|
|
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
|
|
|
|
void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
|
|
|
|
ISD::CondCode CCCode) {
|
|
|
|
MVT::ValueType VT = NewLHS.getValueType();
|
|
|
|
|
|
|
|
// Get the promoted values.
|
|
|
|
NewLHS = GetPromotedOp(NewLHS);
|
|
|
|
NewRHS = GetPromotedOp(NewRHS);
|
|
|
|
|
|
|
|
// If this is an FP compare, the operands have already been extended.
|
|
|
|
if (!MVT::isInteger(NewLHS.getValueType()))
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Otherwise, we have to insert explicit sign or zero extends. Note
|
|
|
|
// that we could insert sign extends for ALL conditions, but zero extend
|
|
|
|
// is cheaper on many machines (an AND instead of two shifts), so prefer
|
|
|
|
// it.
|
|
|
|
switch (CCCode) {
|
|
|
|
default: assert(0 && "Unknown integer comparison!");
|
|
|
|
case ISD::SETEQ:
|
|
|
|
case ISD::SETNE:
|
|
|
|
case ISD::SETUGE:
|
|
|
|
case ISD::SETUGT:
|
|
|
|
case ISD::SETULE:
|
|
|
|
case ISD::SETULT:
|
|
|
|
// ALL of these operations will work if we either sign or zero extend
|
|
|
|
// the operands (including the unsigned comparisons!). Zero extend is
|
|
|
|
// usually a simpler/cheaper operation, so prefer it.
|
|
|
|
NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
|
|
|
|
NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
|
|
|
|
return;
|
|
|
|
case ISD::SETGE:
|
|
|
|
case ISD::SETGT:
|
|
|
|
case ISD::SETLT:
|
|
|
|
case ISD::SETLE:
|
|
|
|
NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
|
|
|
|
DAG.getValueType(VT));
|
|
|
|
NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
|
|
|
|
DAG.getValueType(VT));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_STORE(StoreSDNode *N, unsigned OpNo){
|
|
|
|
SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
|
|
|
|
int SVOffset = N->getSrcValueOffset();
|
|
|
|
unsigned Alignment = N->getAlignment();
|
|
|
|
bool isVolatile = N->isVolatile();
|
|
|
|
|
|
|
|
SDOperand Val = GetPromotedOp(N->getValue()); // Get promoted value.
|
|
|
|
|
|
|
|
assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
|
|
|
|
|
|
|
|
// Truncate the value and store the result.
|
|
|
|
return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
|
2008-01-30 00:15:11 +00:00
|
|
|
SVOffset, N->getMemoryVT(),
|
2007-12-08 20:24:38 +00:00
|
|
|
isVolatile, Alignment);
|
|
|
|
}
|
2008-02-15 19:34:17 +00:00
|
|
|
|
2008-02-24 07:36:03 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) {
|
|
|
|
// The vector type is legal but the element type is not. This implies
|
|
|
|
// that the vector is a power-of-two in length and that the element
|
|
|
|
// type does not have a strange size (eg: it is not i1).
|
|
|
|
MVT::ValueType VecVT = N->getValueType(0);
|
|
|
|
unsigned NumElts = MVT::getVectorNumElements(VecVT);
|
|
|
|
assert(!(NumElts & 1) && "Legal vector of one illegal element?");
|
|
|
|
|
|
|
|
// Build a vector of half the length out of elements of twice the bitwidth.
|
|
|
|
// For example <4 x i16> -> <2 x i32>.
|
|
|
|
MVT::ValueType OldVT = N->getOperand(0).getValueType();
|
|
|
|
MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
|
|
|
|
assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
|
|
|
|
|
|
|
|
std::vector<SDOperand> NewElts;
|
|
|
|
NewElts.reserve(NumElts/2);
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < NumElts; i += 2) {
|
|
|
|
// Combine two successive elements into one promoted element.
|
|
|
|
SDOperand Lo = N->getOperand(i);
|
|
|
|
SDOperand Hi = N->getOperand(i+1);
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
2008-03-11 06:41:14 +00:00
|
|
|
NewElts.push_back(JoinIntegers(Lo, Hi));
|
2008-02-24 07:36:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
|
|
|
|
MVT::getVectorType(NewVT, NewElts.size()),
|
|
|
|
&NewElts[0], NewElts.size());
|
|
|
|
|
|
|
|
// Convert the new vector to the old vector type.
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
|
|
|
|
}
|
|
|
|
|
2008-02-27 10:18:23 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_INSERT_VECTOR_ELT(SDNode *N,
|
|
|
|
unsigned OpNo) {
|
|
|
|
if (OpNo == 1) {
|
|
|
|
// Promote the inserted value. This is valid because the type does not
|
|
|
|
// have to match the vector element type.
|
|
|
|
|
|
|
|
// Check that any extra bits introduced will be truncated away.
|
|
|
|
assert(MVT::getSizeInBits(N->getOperand(1).getValueType()) >=
|
|
|
|
MVT::getSizeInBits(MVT::getVectorElementType(N->getValueType(0))) &&
|
|
|
|
"Type of inserted value narrower than vector element type!");
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
|
|
|
|
GetPromotedOp(N->getOperand(1)),
|
|
|
|
N->getOperand(2));
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(OpNo == 2 && "Different operand and result vector types?");
|
|
|
|
|
|
|
|
// Promote the index.
|
|
|
|
SDOperand Idx = N->getOperand(2);
|
|
|
|
Idx = DAG.getZeroExtendInReg(GetPromotedOp(Idx), Idx.getValueType());
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
|
|
|
|
N->getOperand(1), Idx);
|
|
|
|
}
|
|
|
|
|
2008-02-15 19:34:17 +00:00
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_RET(SDNode *N, unsigned OpNo) {
|
|
|
|
assert(!(OpNo & 1) && "Return values should be legally typed!");
|
|
|
|
assert((N->getNumOperands() & 1) && "Wrong number of operands!");
|
|
|
|
|
|
|
|
// It's a flag. Promote all the flags in one hit, as an optimization.
|
|
|
|
SmallVector<SDOperand, 8> NewValues(N->getNumOperands());
|
|
|
|
NewValues[0] = N->getOperand(0); // The chain
|
|
|
|
for (unsigned i = 1, e = N->getNumOperands(); i < e; i += 2) {
|
|
|
|
// The return value.
|
|
|
|
NewValues[i] = N->getOperand(i);
|
|
|
|
|
|
|
|
// The flag.
|
|
|
|
SDOperand Flag = N->getOperand(i + 1);
|
|
|
|
if (getTypeAction(Flag.getValueType()) == Promote)
|
|
|
|
// The promoted value may have rubbish in the new bits, but that
|
|
|
|
// doesn't matter because those bits aren't queried anyway.
|
|
|
|
Flag = GetPromotedOp(Flag);
|
|
|
|
NewValues[i + 1] = Flag;
|
|
|
|
}
|
|
|
|
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand (N, 0),
|
|
|
|
&NewValues[0], NewValues.size());
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}
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2008-02-27 08:53:44 +00:00
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SDOperand DAGTypeLegalizer::PromoteOperand_MEMBARRIER(SDNode *N) {
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SDOperand NewOps[6];
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NewOps[0] = N->getOperand(0);
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for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
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SDOperand Flag = GetPromotedOp(N->getOperand(i));
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NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
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}
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return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
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array_lengthof(NewOps));
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}
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