2007-12-08 22:37:41 +00:00
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//===-- LegalizeTypesSplit.cpp - Vector Splitting for LegalizeTypes -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-12-08 22:37:41 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements vector splitting support for LegalizeTypes. Vector
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// splitting is the act of changing a computation in an invalid vector type to
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// be a computation in multiple vectors of a smaller type. For example,
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// implementing <128 x f32> operations in terms of two <64 x f32> operations.
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//
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//===----------------------------------------------------------------------===//
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#include "LegalizeTypes.h"
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using namespace llvm;
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2007-12-08 23:08:49 +00:00
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/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a vector
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/// type that needs to be split. This handles non-power of two vectors.
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static void GetSplitDestVTs(MVT::ValueType InVT,
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MVT::ValueType &Lo, MVT::ValueType &Hi) {
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MVT::ValueType NewEltVT = MVT::getVectorElementType(InVT);
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unsigned NumElements = MVT::getVectorNumElements(InVT);
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if ((NumElements & (NumElements-1)) == 0) { // Simple power of two vector.
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NumElements >>= 1;
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Lo = Hi = MVT::getVectorType(NewEltVT, NumElements);
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} else { // Non-power-of-two vectors.
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2007-12-09 17:56:34 +00:00
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unsigned NewNumElts_Lo = 1 << Log2_32(NumElements);
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2007-12-08 23:08:49 +00:00
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unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
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Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
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Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
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}
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}
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2007-12-08 22:37:41 +00:00
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//===----------------------------------------------------------------------===//
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// Result Vector Splitting
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//===----------------------------------------------------------------------===//
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/// SplitResult - This method is called when the specified result of the
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/// specified node is found to need vector splitting. At this point, the node
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/// may also have invalid operands or may have other results that need
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/// legalization, we just know that (at least) one result needs vector
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/// splitting.
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void DAGTypeLegalizer::SplitResult(SDNode *N, unsigned ResNo) {
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2008-03-11 06:41:14 +00:00
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DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
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2007-12-08 22:37:41 +00:00
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SDOperand Lo, Hi;
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#if 0
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// See if the target wants to custom expand this node.
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if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
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TargetLowering::Custom) {
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// If the target wants to, allow it to lower this itself.
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if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
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// Everything that once used N now uses P. We are guaranteed that the
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// result value types of N and the result value types of P match.
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ReplaceNodeWith(N, P);
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return;
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}
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}
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#endif
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "SplitResult #" << ResNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to split the result of this operator!");
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abort();
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2007-12-08 23:58:27 +00:00
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case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
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case ISD::LOAD: SplitRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
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case ISD::BUILD_PAIR: SplitRes_BUILD_PAIR(N, Lo, Hi); break;
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case ISD::INSERT_VECTOR_ELT:SplitRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
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case ISD::VECTOR_SHUFFLE: SplitRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
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case ISD::BUILD_VECTOR: SplitRes_BUILD_VECTOR(N, Lo, Hi); break;
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case ISD::CONCAT_VECTORS: SplitRes_CONCAT_VECTORS(N, Lo, Hi); break;
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case ISD::BIT_CONVERT: SplitRes_BIT_CONVERT(N, Lo, Hi); break;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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case ISD::FNEG:
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case ISD::FABS:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP: SplitRes_UnOp(N, Lo, Hi); break;
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2007-12-08 23:08:49 +00:00
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::FDIV:
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case ISD::FPOW:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::UREM:
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case ISD::SREM:
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2007-12-08 23:58:27 +00:00
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case ISD::FREM: SplitRes_BinOp(N, Lo, Hi); break;
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case ISD::FPOWI: SplitRes_FPOWI(N, Lo, Hi); break;
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case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
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2007-12-08 22:37:41 +00:00
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}
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// If Lo/Hi is null, the sub-method took care of registering results etc.
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if (Lo.Val)
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SetSplitOp(SDOperand(N, ResNo), Lo, Hi);
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}
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2007-12-08 23:08:49 +00:00
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void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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Lo = DAG.getNode(ISD::UNDEF, LoVT);
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Hi = DAG.getNode(ISD::UNDEF, HiVT);
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}
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void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD,
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SDOperand &Lo, SDOperand &Hi) {
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
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SDOperand Ch = LD->getChain();
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SDOperand Ptr = LD->getBasePtr();
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const Value *SV = LD->getSrcValue();
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int SVOffset = LD->getSrcValueOffset();
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unsigned Alignment = LD->getAlignment();
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bool isVolatile = LD->isVolatile();
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Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
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unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8;
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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2008-01-17 07:00:52 +00:00
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DAG.getIntPtrConstant(IncrementSize));
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2007-12-08 23:08:49 +00:00
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SVOffset += IncrementSize;
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Alignment = MinAlign(Alignment, IncrementSize);
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Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
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// Build a factor node to remember that this load is independent of the
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// other one.
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SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceValueWith(SDOperand(LD, 1), TF);
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}
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2007-12-08 23:58:27 +00:00
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void DAGTypeLegalizer::SplitRes_BUILD_PAIR(SDNode *N, SDOperand &Lo,
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SDOperand &Hi) {
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Lo = N->getOperand(0);
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Hi = N->getOperand(1);
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}
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void DAGTypeLegalizer::SplitRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
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SDOperand &Hi) {
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GetSplitOp(N->getOperand(0), Lo, Hi);
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unsigned Index = cast<ConstantSDNode>(N->getOperand(2))->getValue();
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SDOperand ScalarOp = N->getOperand(1);
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unsigned LoNumElts = MVT::getVectorNumElements(Lo.getValueType());
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if (Index < LoNumElts)
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Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, ScalarOp,
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N->getOperand(2));
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else
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Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, ScalarOp,
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2008-03-14 05:23:57 +00:00
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DAG.getIntPtrConstant(Index - LoNumElts));
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2007-12-08 23:58:27 +00:00
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}
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void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// Build the low part.
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SDOperand Mask = N->getOperand(2);
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SmallVector<SDOperand, 16> Ops;
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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MVT::ValueType EltVT = MVT::getVectorElementType(LoVT);
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unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
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unsigned NumElements = Mask.getNumOperands();
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// Insert all of the elements from the input that are needed. We use
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// buildvector of extractelement here because the input vectors will have
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// to be legalized, so this makes the code simpler.
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for (unsigned i = 0; i != LoNumElts; ++i) {
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unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
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SDOperand InVec = N->getOperand(0);
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if (Idx >= NumElements) {
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InVec = N->getOperand(1);
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Idx -= NumElements;
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}
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
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2008-03-14 05:23:57 +00:00
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DAG.getIntPtrConstant(Idx)));
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2007-12-08 23:58:27 +00:00
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}
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Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
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Ops.clear();
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for (unsigned i = LoNumElts; i != NumElements; ++i) {
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unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
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SDOperand InVec = N->getOperand(0);
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if (Idx >= NumElements) {
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InVec = N->getOperand(1);
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Idx -= NumElements;
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}
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
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2008-03-14 05:23:57 +00:00
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DAG.getIntPtrConstant(Idx)));
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2007-12-08 23:58:27 +00:00
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}
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Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
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}
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void DAGTypeLegalizer::SplitRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo,
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SDOperand &Hi) {
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
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SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
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Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
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SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
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Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
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}
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void DAGTypeLegalizer::SplitRes_CONCAT_VECTORS(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// FIXME: Handle non-power-of-two vectors?
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unsigned NumSubvectors = N->getNumOperands() / 2;
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if (NumSubvectors == 1) {
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Lo = N->getOperand(0);
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Hi = N->getOperand(1);
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return;
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}
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
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Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
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SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
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Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
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}
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void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// We know the result is a vector. The input may be either a vector or a
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// scalar value.
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LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
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MVT::ValueType LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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2007-12-08 23:58:27 +00:00
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SDOperand InOp = N->getOperand(0);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
MVT::ValueType InVT = InOp.getValueType();
|
2007-12-08 23:58:27 +00:00
|
|
|
|
2008-03-11 06:41:14 +00:00
|
|
|
// Handle some special cases efficiently.
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
switch (getTypeAction(InVT)) {
|
|
|
|
default:
|
|
|
|
assert(false && "Unknown type action!");
|
|
|
|
case Legal:
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
case FloatToInt:
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
case Promote:
|
|
|
|
case Scalarize:
|
|
|
|
break;
|
|
|
|
case Expand:
|
|
|
|
// A scalar to vector conversion, where the scalar needs expansion.
|
2008-03-11 06:41:14 +00:00
|
|
|
// If the vector is being split in two then we can just convert the
|
|
|
|
// expanded pieces.
|
|
|
|
if (LoVT == HiVT) {
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
GetExpandedOp(InOp, Lo, Hi);
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
|
|
|
|
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case Split:
|
|
|
|
// If the input is a vector that needs to be split, convert each split
|
|
|
|
// piece of the input now.
|
|
|
|
GetSplitOp(InOp, Lo, Hi);
|
2007-12-08 23:58:27 +00:00
|
|
|
Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
|
|
|
|
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
|
|
|
return;
|
|
|
|
}
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2008-03-11 06:41:14 +00:00
|
|
|
// In the general case, convert the input to an integer and split it by hand.
|
|
|
|
MVT::ValueType LoIntVT = MVT::getIntegerType(MVT::getSizeInBits(LoVT));
|
|
|
|
MVT::ValueType HiIntVT = MVT::getIntegerType(MVT::getSizeInBits(HiVT));
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(LoIntVT, HiIntVT);
|
|
|
|
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
|
2008-03-11 06:41:14 +00:00
|
|
|
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
|
|
|
|
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
2007-12-08 23:58:27 +00:00
|
|
|
}
|
|
|
|
|
2007-12-08 23:08:49 +00:00
|
|
|
void DAGTypeLegalizer::SplitRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
|
|
|
|
SDOperand LHSLo, LHSHi;
|
|
|
|
GetSplitOp(N->getOperand(0), LHSLo, LHSHi);
|
|
|
|
SDOperand RHSLo, RHSHi;
|
|
|
|
GetSplitOp(N->getOperand(1), RHSLo, RHSHi);
|
|
|
|
|
|
|
|
Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
|
|
|
|
Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
|
|
|
|
}
|
|
|
|
|
2007-12-08 23:58:27 +00:00
|
|
|
void DAGTypeLegalizer::SplitRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
|
|
|
|
// Get the dest types. This doesn't always match input types, e.g. int_to_fp.
|
|
|
|
MVT::ValueType LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
|
|
|
|
GetSplitOp(N->getOperand(0), Lo, Hi);
|
|
|
|
Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
|
|
|
|
Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
|
|
|
|
}
|
|
|
|
|
|
|
|
void DAGTypeLegalizer::SplitRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
|
|
|
|
GetSplitOp(N->getOperand(0), Lo, Hi);
|
|
|
|
Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
|
|
|
|
Hi = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Hi, N->getOperand(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDOperand &Lo, SDOperand &Hi){
|
|
|
|
SDOperand LL, LH, RL, RH;
|
|
|
|
GetSplitOp(N->getOperand(1), LL, LH);
|
|
|
|
GetSplitOp(N->getOperand(2), RL, RH);
|
|
|
|
|
|
|
|
SDOperand Cond = N->getOperand(0);
|
|
|
|
Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), Cond, LL, RL);
|
|
|
|
Hi = DAG.getNode(ISD::SELECT, LH.getValueType(), Cond, LH, RH);
|
|
|
|
}
|
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Operand Vector Splitting
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// SplitOperand - This method is called when the specified operand of the
|
|
|
|
/// specified node is found to need vector splitting. At this point, all of the
|
|
|
|
/// result types of the node are known to be legal, but other operands of the
|
|
|
|
/// node may need legalization as well as the specified one.
|
|
|
|
bool DAGTypeLegalizer::SplitOperand(SDNode *N, unsigned OpNo) {
|
|
|
|
DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
|
|
|
|
SDOperand Res(0, 0);
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
|
|
|
|
TargetLowering::Custom)
|
|
|
|
Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (Res.Val == 0) {
|
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default:
|
|
|
|
#ifndef NDEBUG
|
|
|
|
cerr << "SplitOperand Op #" << OpNo << ": ";
|
|
|
|
N->dump(&DAG); cerr << "\n";
|
|
|
|
#endif
|
|
|
|
assert(0 && "Do not know how to split this operator's operand!");
|
|
|
|
abort();
|
2007-12-09 00:06:19 +00:00
|
|
|
case ISD::STORE: Res = SplitOp_STORE(cast<StoreSDNode>(N), OpNo); break;
|
|
|
|
case ISD::RET: Res = SplitOp_RET(N, OpNo); break;
|
2008-02-20 17:38:09 +00:00
|
|
|
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
case ISD::BIT_CONVERT: Res = SplitOp_BIT_CONVERT(N); break;
|
|
|
|
|
|
|
|
case ISD::EXTRACT_VECTOR_ELT: Res = SplitOp_EXTRACT_VECTOR_ELT(N); break;
|
|
|
|
case ISD::EXTRACT_SUBVECTOR: Res = SplitOp_EXTRACT_SUBVECTOR(N); break;
|
|
|
|
case ISD::VECTOR_SHUFFLE: Res = SplitOp_VECTOR_SHUFFLE(N, OpNo); break;
|
2007-12-08 22:37:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the result is null, the sub-method took care of registering results etc.
|
|
|
|
if (!Res.Val) return false;
|
|
|
|
|
|
|
|
// If the result is N, the sub-method updated N in place. Check to see if any
|
|
|
|
// operands are new, and if so, mark them.
|
|
|
|
if (Res.Val == N) {
|
|
|
|
// Mark N as new and remark N and its operands. This allows us to correctly
|
|
|
|
// revisit N if it needs another step of promotion and allows us to visit
|
|
|
|
// any new operands to N.
|
2008-02-26 11:21:42 +00:00
|
|
|
ReanalyzeNode(N);
|
2007-12-08 22:37:41 +00:00
|
|
|
return true;
|
|
|
|
}
|
2008-02-26 11:21:42 +00:00
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
|
|
|
|
"Invalid operand expansion");
|
|
|
|
|
|
|
|
ReplaceValueWith(SDOperand(N, 0), Res);
|
|
|
|
return false;
|
|
|
|
}
|
Implement splitting support for store, allowing us to compile:
%f8 = type <8 x float>
define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
%p = load %f8* %P ; <%f8> [#uses=1]
%q = load %f8* %Q ; <%f8> [#uses=1]
%R = add %f8 %p, %q ; <%f8> [#uses=1]
store %f8 %R, %f8* %S
ret void
}
into:
_test_f8:
movaps 16(%rdi), %xmm0
addps 16(%rsi), %xmm0
movaps (%rdi), %xmm1
addps (%rsi), %xmm1
movaps %xmm0, 16(%rdx)
movaps %xmm1, (%rdx)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44725 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-08 23:24:26 +00:00
|
|
|
|
2007-12-09 00:06:19 +00:00
|
|
|
SDOperand DAGTypeLegalizer::SplitOp_STORE(StoreSDNode *N, unsigned OpNo) {
|
Implement splitting support for store, allowing us to compile:
%f8 = type <8 x float>
define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
%p = load %f8* %P ; <%f8> [#uses=1]
%q = load %f8* %Q ; <%f8> [#uses=1]
%R = add %f8 %p, %q ; <%f8> [#uses=1]
store %f8 %R, %f8* %S
ret void
}
into:
_test_f8:
movaps 16(%rdi), %xmm0
addps 16(%rsi), %xmm0
movaps (%rdi), %xmm1
addps (%rsi), %xmm1
movaps %xmm0, 16(%rdx)
movaps %xmm1, (%rdx)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44725 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-08 23:24:26 +00:00
|
|
|
assert(OpNo == 1 && "Can only split the stored value");
|
|
|
|
|
|
|
|
SDOperand Ch = N->getChain();
|
|
|
|
SDOperand Ptr = N->getBasePtr();
|
|
|
|
int SVOffset = N->getSrcValueOffset();
|
|
|
|
unsigned Alignment = N->getAlignment();
|
|
|
|
bool isVol = N->isVolatile();
|
|
|
|
SDOperand Lo, Hi;
|
|
|
|
GetSplitOp(N->getOperand(1), Lo, Hi);
|
|
|
|
|
|
|
|
unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
|
|
|
|
|
|
|
|
Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment);
|
|
|
|
|
|
|
|
// Increment the pointer to the other half.
|
|
|
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
2008-01-17 07:00:52 +00:00
|
|
|
DAG.getIntPtrConstant(IncrementSize));
|
Implement splitting support for store, allowing us to compile:
%f8 = type <8 x float>
define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
%p = load %f8* %P ; <%f8> [#uses=1]
%q = load %f8* %Q ; <%f8> [#uses=1]
%R = add %f8 %p, %q ; <%f8> [#uses=1]
store %f8 %R, %f8* %S
ret void
}
into:
_test_f8:
movaps 16(%rdi), %xmm0
addps 16(%rsi), %xmm0
movaps (%rdi), %xmm1
addps (%rsi), %xmm1
movaps %xmm0, 16(%rdx)
movaps %xmm1, (%rdx)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44725 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-08 23:24:26 +00:00
|
|
|
|
|
|
|
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
|
|
|
isVol, MinAlign(Alignment, IncrementSize));
|
|
|
|
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
|
|
|
|
}
|
|
|
|
|
2007-12-09 00:06:19 +00:00
|
|
|
SDOperand DAGTypeLegalizer::SplitOp_RET(SDNode *N, unsigned OpNo) {
|
|
|
|
assert(N->getNumOperands() == 3 &&"Can only handle ret of one vector so far");
|
|
|
|
// FIXME: Returns of gcc generic vectors larger than a legal vector
|
|
|
|
// type should be returned by reference!
|
|
|
|
SDOperand Lo, Hi;
|
|
|
|
GetSplitOp(N->getOperand(1), Lo, Hi);
|
|
|
|
|
|
|
|
SDOperand Chain = N->getOperand(0); // The chain.
|
|
|
|
SDOperand Sign = N->getOperand(2); // Signness
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Sign, Hi, Sign);
|
|
|
|
}
|
2008-02-20 17:38:09 +00:00
|
|
|
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
SDOperand DAGTypeLegalizer::SplitOp_BIT_CONVERT(SDNode *N) {
|
|
|
|
// For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
|
|
|
|
// end up being split all the way down to individual components. Convert the
|
|
|
|
// split pieces into integers and reassemble.
|
|
|
|
SDOperand Lo, Hi;
|
|
|
|
GetSplitOp(N->getOperand(0), Lo, Hi);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
Lo = BitConvertToInteger(Lo);
|
|
|
|
Hi = BitConvertToInteger(Hi);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
|
2008-03-11 06:41:14 +00:00
|
|
|
JoinIntegers(Lo, Hi));
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) {
|
|
|
|
SDOperand Vec = N->getOperand(0);
|
|
|
|
SDOperand Idx = N->getOperand(1);
|
|
|
|
MVT::ValueType VecVT = Vec.getValueType();
|
|
|
|
|
|
|
|
if (isa<ConstantSDNode>(Idx)) {
|
|
|
|
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
|
|
|
|
assert(IdxVal < MVT::getVectorNumElements(VecVT) &&
|
|
|
|
"Invalid vector index!");
|
|
|
|
|
|
|
|
SDOperand Lo, Hi;
|
|
|
|
GetSplitOp(Vec, Lo, Hi);
|
|
|
|
|
|
|
|
uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
|
|
|
|
|
|
|
|
if (IdxVal < LoElts)
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx);
|
|
|
|
else
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi,
|
|
|
|
DAG.getConstant(IdxVal - LoElts,
|
|
|
|
Idx.getValueType()));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Store the vector to the stack and load back the required element.
|
|
|
|
SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
|
|
|
|
SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
|
|
|
|
|
|
|
|
// Add the offset to the index.
|
|
|
|
MVT::ValueType EltVT = MVT::getVectorElementType(VecVT);
|
|
|
|
unsigned EltSize = MVT::getSizeInBits(EltVT)/8; // FIXME: should be ABI size.
|
|
|
|
Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
|
|
|
|
DAG.getConstant(EltSize, Idx.getValueType()));
|
|
|
|
|
|
|
|
if (MVT::getSizeInBits(Idx.getValueType()) >
|
|
|
|
MVT::getSizeInBits(TLI.getPointerTy()))
|
|
|
|
Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
|
|
|
|
else
|
|
|
|
Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
|
|
|
|
|
|
|
|
StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
|
|
|
|
return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
|
|
|
|
}
|
|
|
|
|
2008-02-20 17:38:09 +00:00
|
|
|
SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) {
|
|
|
|
// We know that the extracted result type is legal. For now, assume the index
|
|
|
|
// is a constant.
|
|
|
|
MVT::ValueType SubVT = N->getValueType(0);
|
|
|
|
SDOperand Idx = N->getOperand(1);
|
|
|
|
SDOperand Lo, Hi;
|
|
|
|
GetSplitOp(N->getOperand(0), Lo, Hi);
|
|
|
|
|
|
|
|
uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
|
|
|
|
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
|
|
|
|
|
|
|
|
if (IdxVal < LoElts) {
|
|
|
|
assert(IdxVal + MVT::getVectorNumElements(SubVT) <= LoElts &&
|
|
|
|
"Extracted subvector crosses vector split!");
|
|
|
|
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
|
|
|
|
} else {
|
|
|
|
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
|
|
|
|
DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
|
|
|
|
}
|
|
|
|
}
|
2008-02-27 13:03:44 +00:00
|
|
|
|
|
|
|
SDOperand DAGTypeLegalizer::SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
|
|
|
|
assert(OpNo == 2 && "Shuffle source type differs from result type?");
|
|
|
|
SDOperand Mask = N->getOperand(2);
|
|
|
|
unsigned MaskLength = MVT::getVectorNumElements(Mask.getValueType());
|
|
|
|
unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
|
|
|
|
unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
|
|
|
|
|
|
|
|
// Look for a legal vector type to place the mask values in.
|
|
|
|
// Note that there may not be *any* legal vector-of-integer
|
|
|
|
// type for which the element type is legal!
|
|
|
|
for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
|
|
|
|
EltVT <= MVT::LAST_INTEGER_VALUETYPE;
|
|
|
|
// Integer values types are consecutively numbered. Exploit this.
|
|
|
|
EltVT = MVT::SimpleValueType(EltVT + 1)) {
|
|
|
|
|
|
|
|
// Is the element type big enough to hold the values?
|
|
|
|
if (MVT::getSizeInBits(EltVT) < MinimumBitWidth)
|
|
|
|
// Nope.
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Is the vector type legal?
|
|
|
|
MVT::ValueType VecVT = MVT::getVectorType(EltVT, MaskLength);
|
|
|
|
if (!isTypeLegal(VecVT))
|
|
|
|
// Nope.
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// If the element type is not legal, find a larger legal type to use for
|
|
|
|
// the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
|
2008-02-27 17:39:13 +00:00
|
|
|
// FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
|
|
|
|
// node where the shuffle mask is a list of integer operands, #2 .. #2+n.
|
2008-02-27 13:03:44 +00:00
|
|
|
for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
|
|
|
|
// Integer values types are consecutively numbered. Exploit this.
|
|
|
|
OpVT = MVT::SimpleValueType(OpVT + 1)) {
|
|
|
|
if (!isTypeLegal(OpVT))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Success! Rebuild the vector using the legal types.
|
|
|
|
SmallVector<SDOperand, 16> Ops(MaskLength);
|
|
|
|
for (unsigned i = 0; i < MaskLength; ++i) {
|
|
|
|
uint64_t Idx =
|
|
|
|
cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
|
|
|
|
Ops[i] = DAG.getConstant(Idx, OpVT);
|
|
|
|
}
|
|
|
|
return DAG.UpdateNodeOperands(SDOperand(N,0),
|
|
|
|
N->getOperand(0), N->getOperand(1),
|
|
|
|
DAG.getNode(ISD::BUILD_VECTOR,
|
|
|
|
VecVT, &Ops[0], Ops.size()));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Continuing is pointless - failure is certain.
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
assert(false && "Failed to find an appropriate mask type!");
|
|
|
|
return SDOperand(N, 0);
|
|
|
|
}
|