mirror of
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377 lines
14 KiB
C++
377 lines
14 KiB
C++
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//=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of TargetFrameInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMFrameInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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/// Move iterator past the next bunch of callee save load / store ops for
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/// the particular spill area (1: integer area 1, 2: integer area 2,
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/// 3: fp area, 0: don't care).
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static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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int Opc1, int Opc2, unsigned Area,
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const ARMSubtarget &STI) {
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while (MBBI != MBB.end() &&
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((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
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MBBI->getOperand(1).isFI()) {
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if (Area != 0) {
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bool Done = false;
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unsigned Category = 0;
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switch (MBBI->getOperand(0).getReg()) {
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case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
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case ARM::LR:
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Category = 1;
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break;
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case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
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Category = STI.isTargetDarwin() ? 2 : 1;
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break;
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case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
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case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
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Category = 3;
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break;
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default:
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Done = true;
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break;
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}
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if (Done || Category != Area)
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break;
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}
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++MBBI;
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}
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}
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static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
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for (unsigned i = 0; CSRegs[i]; ++i)
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if (Reg == CSRegs[i])
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return true;
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return false;
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}
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static bool isCSRestore(MachineInstr *MI,
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const ARMBaseInstrInfo &TII,
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const unsigned *CSRegs) {
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return ((MI->getOpcode() == (int)ARM::VLDRD ||
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MI->getOpcode() == (int)ARM::LDRi12 ||
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MI->getOpcode() == (int)ARM::t2LDRi12) &&
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MI->getOperand(1).isFI() &&
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isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
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}
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static void
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emitSPUpdate(bool isARM,
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MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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DebugLoc dl, const ARMBaseInstrInfo &TII,
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int NumBytes,
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ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
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if (isARM)
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emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
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Pred, PredReg, TII);
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else
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emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
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Pred, PredReg, TII);
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}
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void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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const ARMBaseRegisterInfo *RegInfo =
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static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const ARMBaseInstrInfo &TII =
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*static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
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assert(!AFI->isThumb1OnlyFunction() &&
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"This emitPrologue does not support Thumb1!");
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bool isARM = !AFI->isThumbFunction();
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unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
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unsigned NumBytes = MFI->getStackSize();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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// Determine the sizes of each callee-save spill areas and record which frame
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// belongs to which callee-save spill areas.
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unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
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int FramePtrSpillFI = 0;
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// Allocate the vararg register save area. This is not counted in NumBytes.
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if (VARegSaveSize)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
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if (!AFI->hasStackFrame()) {
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if (NumBytes != 0)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
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return;
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}
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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int FI = CSI[i].getFrameIdx();
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switch (Reg) {
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case ARM::R4:
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case ARM::R5:
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case ARM::R6:
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case ARM::R7:
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case ARM::LR:
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if (Reg == FramePtr)
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FramePtrSpillFI = FI;
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AFI->addGPRCalleeSavedArea1Frame(FI);
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GPRCS1Size += 4;
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break;
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case ARM::R8:
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case ARM::R9:
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case ARM::R10:
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case ARM::R11:
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if (Reg == FramePtr)
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FramePtrSpillFI = FI;
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if (STI.isTargetDarwin()) {
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AFI->addGPRCalleeSavedArea2Frame(FI);
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GPRCS2Size += 4;
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} else {
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AFI->addGPRCalleeSavedArea1Frame(FI);
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GPRCS1Size += 4;
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}
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break;
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default:
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AFI->addDPRCalleeSavedAreaFrame(FI);
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DPRCSSize += 8;
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}
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}
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// Build the new SUBri to adjust SP for integer callee-save spill area 1.
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
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movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
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// Set FP to point to the stack slot that contains the previous FP.
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// For Darwin, FP is R7, which has now been stored in spill area 1.
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// Otherwise, if this is not Darwin, all the callee-saved registers go
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// into spill area 1, including the FP in R11. In either case, it is
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// now safe to emit this assignment.
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bool HasFP = RegInfo->hasFP(MF);
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if (HasFP) {
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unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
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.addFrameIndex(FramePtrSpillFI).addImm(0);
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AddDefaultCC(AddDefaultPred(MIB));
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}
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// Build the new SUBri to adjust SP for integer callee-save spill area 2.
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
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// Build the new SUBri to adjust SP for FP callee-save spill area.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
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// Determine starting offsets of spill areas.
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unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
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unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
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unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
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if (HasFP)
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AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
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NumBytes);
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AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
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AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
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AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
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movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
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NumBytes = DPRCSOffset;
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if (NumBytes) {
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// Adjust SP after all the callee-save spills.
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
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if (HasFP)
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AFI->setShouldRestoreSPFromFP(true);
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}
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if (STI.isTargetELF() && RegInfo->hasFP(MF)) {
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MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
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AFI->getFramePtrSpillOffset());
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AFI->setShouldRestoreSPFromFP(true);
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}
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AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
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AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
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AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
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// If we need dynamic stack realignment, do it here. Be paranoid and make
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// sure if we also have VLAs, we have a base pointer for frame access.
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if (RegInfo->needsStackRealignment(MF)) {
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unsigned MaxAlign = MFI->getMaxAlignment();
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assert (!AFI->isThumb1OnlyFunction());
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if (!AFI->isThumbFunction()) {
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// Emit bic sp, sp, MaxAlign
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
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TII.get(ARM::BICri), ARM::SP)
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.addReg(ARM::SP, RegState::Kill)
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.addImm(MaxAlign-1)));
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} else {
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// We cannot use sp as source/dest register here, thus we're emitting the
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// following sequence:
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// mov r4, sp
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// bic r4, r4, MaxAlign
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// mov sp, r4
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// FIXME: It will be better just to find spare register here.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
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.addReg(ARM::SP, RegState::Kill);
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
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TII.get(ARM::t2BICri), ARM::R4)
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.addReg(ARM::R4, RegState::Kill)
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.addImm(MaxAlign-1)));
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
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.addReg(ARM::R4, RegState::Kill);
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}
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AFI->setShouldRestoreSPFromFP(true);
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}
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// If we need a base pointer, set it up here. It's whatever the value
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// of the stack pointer is at this point. Any variable size objects
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// will be allocated after this, so we can still use the base pointer
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// to reference locals.
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if (RegInfo->hasBasePointer(MF)) {
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if (isARM)
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BuildMI(MBB, MBBI, dl,
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TII.get(ARM::MOVr), RegInfo->getBaseRegister())
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.addReg(ARM::SP)
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.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
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else
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BuildMI(MBB, MBBI, dl,
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TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
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.addReg(ARM::SP);
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}
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// If the frame has variable sized objects then the epilogue must restore
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// the sp from fp.
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if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
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AFI->setShouldRestoreSPFromFP(true);
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}
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void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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assert(MBBI->getDesc().isReturn() &&
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"Can only insert epilog into returning blocks");
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unsigned RetOpcode = MBBI->getOpcode();
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DebugLoc dl = MBBI->getDebugLoc();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
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const ARMBaseInstrInfo &TII =
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*static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
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assert(!AFI->isThumb1OnlyFunction() &&
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"This emitEpilogue does not support Thumb1!");
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bool isARM = !AFI->isThumbFunction();
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unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
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int NumBytes = (int)MFI->getStackSize();
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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if (!AFI->hasStackFrame()) {
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if (NumBytes != 0)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
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} else {
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// Unwind MBBI to point to first LDR / VLDRD.
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const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
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if (MBBI != MBB.begin()) {
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do
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--MBBI;
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while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
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if (!isCSRestore(MBBI, TII, CSRegs))
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++MBBI;
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}
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// Move SP to start of FP callee save spill area.
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NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
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AFI->getGPRCalleeSavedArea2Size() +
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AFI->getDPRCalleeSavedAreaSize());
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// Reset SP based on frame pointer only if the stack frame extends beyond
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// frame pointer stack slot or target is ELF and the function has FP.
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if (AFI->shouldRestoreSPFromFP()) {
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NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
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if (NumBytes) {
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if (isARM)
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emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
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ARMCC::AL, 0, TII);
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else
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emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
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ARMCC::AL, 0, TII);
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} else {
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// Thumb2 or ARM.
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if (isARM)
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BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
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.addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
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else
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
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.addReg(FramePtr);
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}
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} else if (NumBytes)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
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// Move SP to start of integer callee save spill area 2.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
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// Move SP to start of integer callee save spill area 1.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
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// Move SP to SP upon entry to the function.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
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}
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if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
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RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
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// Tail call return: adjust the stack pointer and jump to callee.
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MBBI = prior(MBB.end());
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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// Jump to label or value in register.
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if (RetOpcode == ARM::TCRETURNdi) {
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BuildMI(MBB, MBBI, dl,
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TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
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JumpTarget.getTargetFlags());
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} else if (RetOpcode == ARM::TCRETURNdiND) {
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BuildMI(MBB, MBBI, dl,
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TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
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JumpTarget.getTargetFlags());
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} else if (RetOpcode == ARM::TCRETURNri) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
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addReg(JumpTarget.getReg(), RegState::Kill);
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} else if (RetOpcode == ARM::TCRETURNriND) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
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addReg(JumpTarget.getReg(), RegState::Kill);
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}
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MachineInstr *NewMI = prior(MBBI);
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for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
|
||
|
NewMI->addOperand(MBBI->getOperand(i));
|
||
|
|
||
|
// Delete the pseudo instruction TCRETURN.
|
||
|
MBB.erase(MBBI);
|
||
|
}
|
||
|
|
||
|
if (VARegSaveSize)
|
||
|
emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
|
||
|
}
|