2012-09-14 20:26:46 +00:00
|
|
|
//===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file defines a wrapper around MCSchedModel that allows the interface to
|
|
|
|
// benefit from information currently only available in TargetInstrInfo.
|
2012-09-14 20:27:25 +00:00
|
|
|
// Ideally, the scheduling interface would be fully defined in the MC layer.
|
2012-09-14 20:26:46 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-01-10 00:45:19 +00:00
|
|
|
#ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
|
|
|
|
#define LLVM_CODEGEN_TARGETSCHEDULE_H
|
2012-09-14 20:26:46 +00:00
|
|
|
|
2012-11-06 07:10:38 +00:00
|
|
|
#include "llvm/ADT/SmallVector.h"
|
2012-12-03 17:02:12 +00:00
|
|
|
#include "llvm/MC/MCInstrItineraries.h"
|
|
|
|
#include "llvm/MC/MCSchedule.h"
|
|
|
|
#include "llvm/Target/TargetSubtargetInfo.h"
|
2012-09-14 20:26:46 +00:00
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
|
|
|
|
class TargetRegisterInfo;
|
|
|
|
class TargetSubtargetInfo;
|
|
|
|
class TargetInstrInfo;
|
|
|
|
class MachineInstr;
|
|
|
|
|
|
|
|
/// Provide an instruction scheduling machine model to CodeGen passes.
|
|
|
|
class TargetSchedModel {
|
|
|
|
// For efficiency, hold a copy of the statically defined MCSchedModel for this
|
|
|
|
// processor.
|
|
|
|
MCSchedModel SchedModel;
|
|
|
|
InstrItineraryData InstrItins;
|
|
|
|
const TargetSubtargetInfo *STI;
|
|
|
|
const TargetInstrInfo *TII;
|
2012-11-06 07:10:38 +00:00
|
|
|
|
|
|
|
SmallVector<unsigned, 16> ResourceFactors;
|
|
|
|
unsigned MicroOpFactor; // Multiply to normalize microops to resource units.
|
|
|
|
unsigned ResourceLCM; // Resource units per cycle. Latency normalization factor.
|
2012-09-14 20:26:46 +00:00
|
|
|
public:
|
2014-04-14 00:51:57 +00:00
|
|
|
TargetSchedModel(): STI(nullptr), TII(nullptr) {}
|
2012-09-14 20:26:46 +00:00
|
|
|
|
2012-10-09 23:44:29 +00:00
|
|
|
/// \brief Initialize the machine model for instruction scheduling.
|
|
|
|
///
|
|
|
|
/// The machine model API keeps a copy of the top-level MCSchedModel table
|
|
|
|
/// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
|
|
|
|
/// dynamic properties.
|
2012-09-14 20:26:46 +00:00
|
|
|
void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
|
|
|
|
const TargetInstrInfo *tii);
|
|
|
|
|
2012-11-06 07:10:38 +00:00
|
|
|
/// Return the MCSchedClassDesc for this instruction.
|
|
|
|
const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
|
|
|
|
|
2012-10-09 23:44:29 +00:00
|
|
|
/// \brief TargetInstrInfo getter.
|
2012-09-14 20:26:46 +00:00
|
|
|
const TargetInstrInfo *getInstrInfo() const { return TII; }
|
|
|
|
|
2012-10-09 23:44:29 +00:00
|
|
|
/// \brief Return true if this machine model includes an instruction-level
|
|
|
|
/// scheduling model.
|
|
|
|
///
|
|
|
|
/// This is more detailed than the course grain IssueWidth and default
|
2012-09-14 20:26:46 +00:00
|
|
|
/// latency properties, but separate from the per-cycle itinerary data.
|
2012-10-09 23:44:26 +00:00
|
|
|
bool hasInstrSchedModel() const;
|
2012-09-14 20:26:46 +00:00
|
|
|
|
2012-10-10 05:43:09 +00:00
|
|
|
const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
|
|
|
|
|
2012-10-09 23:44:29 +00:00
|
|
|
/// \brief Return true if this machine model includes cycle-to-cycle itinerary
|
|
|
|
/// data.
|
|
|
|
///
|
|
|
|
/// This models scheduling at each stage in the processor pipeline.
|
2012-10-09 23:44:26 +00:00
|
|
|
bool hasInstrItineraries() const;
|
2012-09-18 04:03:34 +00:00
|
|
|
|
2012-10-10 05:43:09 +00:00
|
|
|
const InstrItineraryData *getInstrItineraries() const {
|
|
|
|
if (hasInstrItineraries())
|
|
|
|
return &InstrItins;
|
2014-04-14 00:51:57 +00:00
|
|
|
return nullptr;
|
2012-10-10 05:43:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Identify the processor corresponding to the current subtarget.
|
|
|
|
unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
|
|
|
|
|
|
|
|
/// \brief Maximum number of micro-ops that may be scheduled per cycle.
|
|
|
|
unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
|
|
|
|
|
|
|
|
/// \brief Return the number of issue slots required for this MI.
|
2012-11-06 07:10:38 +00:00
|
|
|
unsigned getNumMicroOps(const MachineInstr *MI,
|
2014-04-14 00:51:57 +00:00
|
|
|
const MCSchedClassDesc *SC = nullptr) const;
|
2012-11-06 07:10:38 +00:00
|
|
|
|
|
|
|
/// \brief Get the number of kinds of resources for this target.
|
|
|
|
unsigned getNumProcResourceKinds() const {
|
|
|
|
return SchedModel.getNumProcResourceKinds();
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Get a processor resource by ID for convenience.
|
|
|
|
const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
|
|
|
|
return SchedModel.getProcResource(PIdx);
|
|
|
|
}
|
|
|
|
|
2013-12-07 05:59:44 +00:00
|
|
|
#ifndef NDEBUG
|
|
|
|
const char *getResourceName(unsigned PIdx) const {
|
|
|
|
if (!PIdx)
|
|
|
|
return "MOps";
|
|
|
|
return SchedModel.getProcResource(PIdx)->Name;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-11-06 07:10:38 +00:00
|
|
|
typedef const MCWriteProcResEntry *ProcResIter;
|
|
|
|
|
|
|
|
// \brief Get an iterator into the processor resources consumed by this
|
|
|
|
// scheduling class.
|
|
|
|
ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
|
|
|
|
// The subtarget holds a single resource table for all processors.
|
|
|
|
return STI->getWriteProcResBegin(SC);
|
|
|
|
}
|
|
|
|
ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
|
|
|
|
return STI->getWriteProcResEnd(SC);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Multiply the number of units consumed for a resource by this factor
|
|
|
|
/// to normalize it relative to other resources.
|
|
|
|
unsigned getResourceFactor(unsigned ResIdx) const {
|
|
|
|
return ResourceFactors[ResIdx];
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Multiply number of micro-ops by this factor to normalize it
|
|
|
|
/// relative to other resources.
|
|
|
|
unsigned getMicroOpFactor() const {
|
|
|
|
return MicroOpFactor;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Multiply cycle count by this factor to normalize it relative to
|
|
|
|
/// other resources. This is the number of resource units per cycle.
|
|
|
|
unsigned getLatencyFactor() const {
|
|
|
|
return ResourceLCM;
|
|
|
|
}
|
2012-10-10 05:43:09 +00:00
|
|
|
|
2013-06-15 04:49:57 +00:00
|
|
|
/// \brief Number of micro-ops that may be buffered for OOO execution.
|
|
|
|
unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
|
|
|
|
|
|
|
|
/// \brief Number of resource units that may be buffered for OOO execution.
|
|
|
|
/// \return The buffer size in resource units or -1 for unlimited.
|
|
|
|
int getResourceBufferSize(unsigned PIdx) const {
|
|
|
|
return SchedModel.getProcResource(PIdx)->BufferSize;
|
|
|
|
}
|
|
|
|
|
2012-10-09 23:44:29 +00:00
|
|
|
/// \brief Compute operand latency based on the available machine model.
|
|
|
|
///
|
2013-06-15 04:49:57 +00:00
|
|
|
/// Compute and return the latency of the given data dependent def and use
|
2012-10-09 23:44:29 +00:00
|
|
|
/// when the operand indices are already known. UseMI may be NULL for an
|
|
|
|
/// unknown user.
|
2012-09-18 04:03:34 +00:00
|
|
|
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
|
2013-06-15 04:49:57 +00:00
|
|
|
const MachineInstr *UseMI, unsigned UseOperIdx)
|
|
|
|
const;
|
2012-09-14 20:26:46 +00:00
|
|
|
|
2012-10-09 23:44:32 +00:00
|
|
|
/// \brief Compute the instruction latency based on the available machine
|
|
|
|
/// model.
|
|
|
|
///
|
|
|
|
/// Compute and return the expected latency of this instruction independent of
|
2014-01-24 17:20:08 +00:00
|
|
|
/// a particular use. computeOperandLatency is the preferred API, but this is
|
2012-10-09 23:44:32 +00:00
|
|
|
/// occasionally useful to help estimate instruction cost.
|
2013-09-30 15:28:56 +00:00
|
|
|
///
|
|
|
|
/// If UseDefaultDefLatency is false and no new machine sched model is
|
|
|
|
/// present this method falls back to TII->getInstrLatency with an empty
|
|
|
|
/// instruction itinerary (this is so we preserve the previous behavior of the
|
|
|
|
/// if converter after moving it to TargetSchedModel).
|
|
|
|
unsigned computeInstrLatency(const MachineInstr *MI,
|
|
|
|
bool UseDefaultDefLatency = true) const;
|
2012-10-09 23:44:32 +00:00
|
|
|
|
2012-10-10 05:43:09 +00:00
|
|
|
/// \brief Output dependency latency of a pair of defs of the same register.
|
|
|
|
///
|
|
|
|
/// This is typically one cycle.
|
|
|
|
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
|
|
|
|
const MachineInstr *DepMI) const;
|
2012-09-14 20:26:46 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
} // namespace llvm
|
|
|
|
|
|
|
|
#endif
|