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llvm-6502/test/Analysis/CostModel/ARM/select.ll

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ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios6.0.0"
; CHECK: casts
define void @casts() {
; Scalar values
; CHECK: cost of 1 {{.*}} select
%v1 = select i1 undef, i8 undef, i8 undef
; CHECK: cost of 1 {{.*}} select
%v2 = select i1 undef, i16 undef, i16 undef
; CHECK: cost of 1 {{.*}} select
%v3 = select i1 undef, i32 undef, i32 undef
; CHECK: cost of 2 {{.*}} select
%v4 = select i1 undef, i64 undef, i64 undef
; CHECK: cost of 1 {{.*}} select
%v5 = select i1 undef, float undef, float undef
; CHECK: cost of 1 {{.*}} select
%v6 = select i1 undef, double undef, double undef
; Vector values
; CHECK: cost of 1 {{.*}} select
%v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef
ARM cost model: Fix costs for some vector selects I was too pessimistic in r177105. Vector selects that fit into a legal register type lower just fine. I was mislead by the code fragment that I was using. The stores/loads that I saw in those cases came from lowering the conditional off an address. Changing the code fragment to: %T0_3 = type <8 x i18> %T1_3 = type <8 x i1> define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2, %T1_3* %blend, %T0_3* %storeaddr) { %v0 = load %T0_3* %loadaddr %v1 = load %T0_3* %loadaddr2 ==> FROM: ;%c = load %T1_3* %blend ==> TO: %c = icmp slt %T0_3 %v0, %v1 ==> USE: %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1 store %T0_3 %r, %T0_3* %storeaddr ret void } revealed this mistake. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 18:31:01 +00:00
; CHECK: cost of 1 {{.*}} select
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
%v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef
ARM cost model: Fix costs for some vector selects I was too pessimistic in r177105. Vector selects that fit into a legal register type lower just fine. I was mislead by the code fragment that I was using. The stores/loads that I saw in those cases came from lowering the conditional off an address. Changing the code fragment to: %T0_3 = type <8 x i18> %T1_3 = type <8 x i1> define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2, %T1_3* %blend, %T0_3* %storeaddr) { %v0 = load %T0_3* %loadaddr %v1 = load %T0_3* %loadaddr2 ==> FROM: ;%c = load %T1_3* %blend ==> TO: %c = icmp slt %T0_3 %v0, %v1 ==> USE: %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1 store %T0_3 %r, %T0_3* %storeaddr ret void } revealed this mistake. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 18:31:01 +00:00
; CHECK: cost of 1 {{.*}} select
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
%v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef
ARM cost model: Fix costs for some vector selects I was too pessimistic in r177105. Vector selects that fit into a legal register type lower just fine. I was mislead by the code fragment that I was using. The stores/loads that I saw in those cases came from lowering the conditional off an address. Changing the code fragment to: %T0_3 = type <8 x i18> %T1_3 = type <8 x i1> define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2, %T1_3* %blend, %T0_3* %storeaddr) { %v0 = load %T0_3* %loadaddr %v1 = load %T0_3* %loadaddr2 ==> FROM: ;%c = load %T1_3* %blend ==> TO: %c = icmp slt %T0_3 %v0, %v1 ==> USE: %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1 store %T0_3 %r, %T0_3* %storeaddr ret void } revealed this mistake. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 18:31:01 +00:00
; CHECK: cost of 1 {{.*}} select
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
%v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef
; CHECK: cost of 1 {{.*}} select
%v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef
ARM cost model: Fix costs for some vector selects I was too pessimistic in r177105. Vector selects that fit into a legal register type lower just fine. I was mislead by the code fragment that I was using. The stores/loads that I saw in those cases came from lowering the conditional off an address. Changing the code fragment to: %T0_3 = type <8 x i18> %T1_3 = type <8 x i1> define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2, %T1_3* %blend, %T0_3* %storeaddr) { %v0 = load %T0_3* %loadaddr %v1 = load %T0_3* %loadaddr2 ==> FROM: ;%c = load %T1_3* %blend ==> TO: %c = icmp slt %T0_3 %v0, %v1 ==> USE: %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1 store %T0_3 %r, %T0_3* %storeaddr ret void } revealed this mistake. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 18:31:01 +00:00
; CHECK: cost of 1 {{.*}} select
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
%v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef
ARM cost model: Fix costs for some vector selects I was too pessimistic in r177105. Vector selects that fit into a legal register type lower just fine. I was mislead by the code fragment that I was using. The stores/loads that I saw in those cases came from lowering the conditional off an address. Changing the code fragment to: %T0_3 = type <8 x i18> %T1_3 = type <8 x i1> define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2, %T1_3* %blend, %T0_3* %storeaddr) { %v0 = load %T0_3* %loadaddr %v1 = load %T0_3* %loadaddr2 ==> FROM: ;%c = load %T1_3* %blend ==> TO: %c = icmp slt %T0_3 %v0, %v1 ==> USE: %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1 store %T0_3 %r, %T0_3* %storeaddr ret void } revealed this mistake. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 18:31:01 +00:00
; CHECK: cost of 1 {{.*}} select
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
%v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef
ARM cost model: Increase cost of some vector selects we do terrible on By terrible I mean we store/load from the stack. This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update) where we decide to vectorize a loop with a VF of 8 resulting in a 25% degradation on a cortex-a8. LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32 LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32 The bug that tracks the CodeGen part is PR14868. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:17:02 +00:00
; CHECK: cost of 40 {{.*}} select
%v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
; CHECK: cost of 1 {{.*}} select
%v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef
; CHECK: cost of 1 {{.*}} select
%v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef
ARM cost model: Increase cost of some vector selects we do terrible on By terrible I mean we store/load from the stack. This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update) where we decide to vectorize a loop with a VF of 8 resulting in a 25% degradation on a cortex-a8. LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32 LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32 The bug that tracks the CodeGen part is PR14868. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:17:02 +00:00
; CHECK: cost of 41 {{.*}} select
%v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef
; CHECK: cost of 82 {{.*}} select
%v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
; CHECK: cost of 1 {{.*}} select
%v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef
ARM cost model: Increase cost of some vector selects we do terrible on By terrible I mean we store/load from the stack. This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update) where we decide to vectorize a loop with a VF of 8 resulting in a 25% degradation on a cortex-a8. LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32 LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32 The bug that tracks the CodeGen part is PR14868. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 19:17:02 +00:00
; CHECK: cost of 19 {{.*}} select
%v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef
; CHECK: cost of 50 {{.*}} select
%v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef
; CHECK: cost of 100 {{.*}} select
%v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
; CHECK: cost of 1 {{.*}} select
%v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef
; CHECK: cost of 1 {{.*}} select
%v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef
; CHECK: cost of 1 {{.*}} select
%v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef
Fixes ARM LNT bot from SLP change in O3 This patch fixes the multiple breakages on ARM test-suite after the SLP vectorizer was introduced by default on O3. The problem was an illegal vector type on ARMTTI::getCmpSelInstrCost() <3 x i1> which is not simple. The guard protects this code from breaking (cause of the problems) but doesn't fix the issue that is generating the odd vector in the first place, which also needs to be investigated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187658 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 17:10:04 +00:00
; odd vectors get legalized and should have similar costs
; CHECK: cost of 1 {{.*}} select
%v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef
; CHECK: cost of 1 {{.*}} select
%v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef
; CHECK: cost of 4 {{.*}} select
%v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef
ARM cost model: Add costs for vector selects Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 16:10:15 +00:00
ret void
}
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