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llvm-6502/test/MC/ARM/basic-thumb2-instructions-v8.s

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Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 14:14:19 +00:00
@ New ARMv8 T32 encodings
Test cleanup for v8 instructions Add some missing tests, factor out a test not specific to v8 into its own file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 14:16:09 +00:00
@ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 14:14:19 +00:00
@ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ HLT
hlt #0
hlt #63
@ CHECK-V8: hlt #0 @ encoding: [0x80,0xba]
@ CHECK-V8: hlt #63 @ encoding: [0xbf,0xba]
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ In IT block
it pl
hlt #24
@ CHECK-V8: it pl @ encoding: [0x58,0xbf]
@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
@ CHECK-V7: error: instruction requires: armv8
@ Can accept AL condition code
hltal #24
@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
@ CHECK-V7: error: instruction requires: armv8
@ DCPS{1,2,3}
dcps1
dcps2
dcps3
@ CHECK-V8: dcps1 @ encoding: [0x8f,0xf7,0x01,0x80]
@ CHECK-V8: dcps2 @ encoding: [0x8f,0xf7,0x02,0x80]
@ CHECK-V8: dcps3 @ encoding: [0x8f,0xf7,0x03,0x80]
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
[ARMv8] Add some missing tests for DSB/DMB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 16:05:45 +00:00
@------------------------------------------------------------------------------
@ DMB (v8 barriers)
@------------------------------------------------------------------------------
dmb ishld
dmb oshld
dmb nshld
dmb ld
@ CHECK-V8: dmb ishld @ encoding: [0xbf,0xf3,0x59,0x8f]
@ CHECK-V8: dmb oshld @ encoding: [0xbf,0xf3,0x51,0x8f]
@ CHECK-V8: dmb nshld @ encoding: [0xbf,0xf3,0x55,0x8f]
@ CHECK-V8: dmb ld @ encoding: [0xbf,0xf3,0x5d,0x8f]
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@------------------------------------------------------------------------------
@ DSB (v8 barriers)
@------------------------------------------------------------------------------
dsb ishld
dsb oshld
dsb nshld
dsb ld
@ CHECK-V8: dsb ishld @ encoding: [0xbf,0xf3,0x49,0x8f]
@ CHECK-V8: dsb oshld @ encoding: [0xbf,0xf3,0x41,0x8f]
@ CHECK-V8: dsb nshld @ encoding: [0xbf,0xf3,0x45,0x8f]
@ CHECK-V8: dsb ld @ encoding: [0xbf,0xf3,0x4d,0x8f]
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
@ CHECK-V7: error: invalid operand for instruction
Test cleanup for v8 instructions Add some missing tests, factor out a test not specific to v8 into its own file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 14:16:09 +00:00
@ CHECK-V7: error: invalid operand for instruction
[ARM] Introduce the 'sevl' instruction in ARMv8. This also removes the restriction on the immediate field of the 'hint' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:39:11 +00:00
@------------------------------------------------------------------------------
@ SEVL
@------------------------------------------------------------------------------
sevl
sevl.w
it ge
sevlge
@ CHECK-V8: sevl @ encoding: [0x50,0xbf]
@ CHECK-V8: sevl.w @ encoding: [0xaf,0xf3,0x05,0x80]
@ CHECK-V8: it ge @ encoding: [0xa8,0xbf]
@ CHECK-V8: sevlge @ encoding: [0x50,0xbf]
Test cleanup for v8 instructions Add some missing tests, factor out a test not specific to v8 into its own file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 14:16:09 +00:00
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error:
@ CHECK-V7: error: instruction requires: armv8
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