llvm-6502/test/CodeGen/AArch64/paired-load.ll

; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linux-gnu"

; Ensure we're generating ldp instructions instead of ldr Q.
; CHECK: ldp
; CHECK: stp
define void @f(i64* %p, i64* %q) {
  %addr2 = getelementptr i64* %q, i32 1
  %addr = getelementptr i64* %p, i32 1
  %x = load i64* %p
  %y = load i64* %addr
  store i64 %x, i64* %q
  store i64 %y, i64* %addr2
  ret void
}
[AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load is not a good transform when paired loads are available. The combiner was creating Q-register loads and stores, which then had to be spilled because there are no callee-save Q registers! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214634 91177308-0d34-0410-b5e6-96231b3b80d8 2014-08-02 14:51:24 +00:00			`; RUN: llc < %s \| FileCheck %s`
			`target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"`
Update test to use a more modern AArch64 triple, as requested by Renato. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214637 91177308-0d34-0410-b5e6-96231b3b80d8 2014-08-02 17:15:11 +00:00			`target triple = "aarch64-linux-gnu"`
[AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load is not a good transform when paired loads are available. The combiner was creating Q-register loads and stores, which then had to be spilled because there are no callee-save Q registers! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214634 91177308-0d34-0410-b5e6-96231b3b80d8 2014-08-02 14:51:24 +00:00
			`; Ensure we're generating ldp instructions instead of ldr Q.`
			`; CHECK: ldp`
			`; CHECK: stp`
			`define void @f(i64* %p, i64* %q) {`
			`%addr2 = getelementptr i64* %q, i32 1`
			`%addr = getelementptr i64* %p, i32 1`
			`%x = load i64* %p`
			`%y = load i64* %addr`
			`store i64 %x, i64* %q`
			`store i64 %y, i64* %addr2`
			`ret void`
			`}`