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llvm-6502/test/MC/Disassembler/ARM64/system.txt

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ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
#-----------------------------------------------------------------------------
# Hint encodings
#-----------------------------------------------------------------------------
0x1f 0x20 0x03 0xd5
# CHECK: nop
0x9f 0x20 0x03 0xd5
# CHECK: sev
0xbf 0x20 0x03 0xd5
# CHECK: sevl
0x5f 0x20 0x03 0xd5
# CHECK: wfe
0x7f 0x20 0x03 0xd5
# CHECK: wfi
0x3f 0x20 0x03 0xd5
# CHECK: yield
#-----------------------------------------------------------------------------
# Single-immediate operand instructions
#-----------------------------------------------------------------------------
0x5f 0x3a 0x03 0xd5
# CHECK: clrex #10
0xdf 0x3f 0x03 0xd5
# CHECK: isb{{$}}
[ARM64] Correctly disassemble ISB operand as ISB not DBarrier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205897 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:54 +00:00
0xdf 0x31 0x03 0xd5
# CHECK: isb #1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0xbf 0x33 0x03 0xd5
# CHECK: dmb osh
0x9f 0x37 0x03 0xd5
# CHECK: dsb nsh
[ARM64] Change SYS without a register to an alias to make disassembling more consistant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:58 +00:00
0x3f 0x76 0x08 0xd5
# CHECK: dc ivac
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
#-----------------------------------------------------------------------------
# Generic system instructions
#-----------------------------------------------------------------------------
0xff 0x05 0x0a 0xd5
0xe7 0x6a 0x0f 0xd5
0xf4 0x3f 0x2e 0xd5
0xbf 0x40 0x00 0xd5
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:36 +00:00
0x00 0xb0 0x18 0xd5
0x00 0xb0 0x38 0xd5
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# CHECK: sys #2, c0, c5, #7
# CHECK: sys #7, c6, c10, #7, x7
# CHECK: sysl x20, #6, c3, c15, #7
[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:42 +00:00
# CHECK: msr SPSEL, #0
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:36 +00:00
# CHECK: msr S3_0_C11_C0_0, x0
# CHECK: mrs x0, S3_0_C11_C0_0
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x40 0xc0 0x1e 0xd5
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:36 +00:00
0x40 0xc0 0x1c 0xd5
0x40 0xc0 0x18 0xd5
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# CHECK: msr RMR_EL3, x0
# CHECK: msr RMR_EL2, x0
# CHECK: msr RMR_EL1, x0
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