llvm-6502/test/CodeGen/X86/avx-bitcast.ll

; RUN: llc < %s -O0 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s

; CHECK: vmovsd (%
; CHECK-NEXT: vmovq %xmm
define i64 @bitcasti64tof64() {
  %a = load double* undef
  %b = bitcast double %a to i64
  ret i64 %b
}
Add a AVX version of a simple i64 -> f64 bitcast. This could be triggered using llc with -O0, which wouldn't let it be folded and expose the lack of this pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8 2011-09-08 21:52:33 +00:00			`; RUN: llc < %s -O0 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx \| FileCheck %s`

			`; CHECK: vmovsd (%`
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8 2013-10-08 05:53:50 +00:00			`; CHECK-NEXT: vmovq %xmm`
Add a AVX version of a simple i64 -> f64 bitcast. This could be triggered using llc with -O0, which wouldn't let it be folded and expose the lack of this pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8 2011-09-08 21:52:33 +00:00			`define i64 @bitcasti64tof64() {`
			`%a = load double* undef`
			`%b = bitcast double %a to i64`
			`ret i64 %b`
			`}`