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llvm-6502/test/CodeGen/AArch64/dp1.ll

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Add explicit triples to AArch64 tests Only Linux is supported at the moment, and other platforms quickly fault. As a result these tests would fail on non-Linux hosts. It may be worth making the tests more generic again as more platforms are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 11:40:47 +00:00
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
Add AArch64 as an experimental target. This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 12:12:40 +00:00
@var32 = global i32 0
@var64 = global i64 0
define void @rev_i32() {
; CHECK: rev_i32:
%val0_tmp = load i32* @var32
%val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val1_tmp, i32* @var32
ret void
}
define void @rev_i64() {
; CHECK: rev_i64:
%val0_tmp = load i64* @var64
%val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val1_tmp, i64* @var64
ret void
}
define void @rev32_i64() {
; CHECK: rev32_i64:
%val0_tmp = load i64* @var64
%val1_tmp = shl i64 %val0_tmp, 32
%val5_tmp = sub i64 64, 32
%val2_tmp = lshr i64 %val0_tmp, %val5_tmp
%val3_tmp = or i64 %val1_tmp, %val2_tmp
%val4_tmp = call i64 @llvm.bswap.i64(i64 %val3_tmp)
; CHECK: rev32 {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64
ret void
}
define void @rev16_i32() {
; CHECK: rev16_i32:
%val0_tmp = load i32* @var32
%val1_tmp = shl i32 %val0_tmp, 16
%val2_tmp = lshr i32 %val0_tmp, 16
%val3_tmp = or i32 %val1_tmp, %val2_tmp
%val4_tmp = call i32 @llvm.bswap.i32(i32 %val3_tmp)
; CHECK: rev16 {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @clz_zerodef_i32() {
; CHECK: clz_zerodef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @clz_zerodef_i64() {
; CHECK: clz_zerodef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64
ret void
}
define void @clz_zeroundef_i32() {
; CHECK: clz_zeroundef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @clz_zeroundef_i64() {
; CHECK: clz_zeroundef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64
ret void
}
define void @cttz_zerodef_i32() {
; CHECK: cttz_zerodef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @cttz_zerodef_i64() {
; CHECK: cttz_zerodef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
store volatile i64 %val4_tmp, i64* @var64
ret void
}
define void @cttz_zeroundef_i32() {
; CHECK: cttz_zeroundef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @cttz_zeroundef_i64() {
; CHECK: cttz_zeroundef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
store volatile i64 %val4_tmp, i64* @var64
ret void
}
; These two are just compilation tests really: the operation's set to Expand in
; ISelLowering.
define void @ctpop_i32() {
; CHECK: ctpop_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
store volatile i32 %val4_tmp, i32* @var32
ret void
}
define void @ctpop_i64() {
; CHECK: ctpop_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
store volatile i64 %val4_tmp, i64* @var64
ret void
}
declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64)
declare i32 @llvm.ctlz.i32 (i32, i1)
declare i64 @llvm.ctlz.i64 (i64, i1)
declare i32 @llvm.cttz.i32 (i32, i1)
declare i64 @llvm.cttz.i64 (i64, i1)
declare i32 @llvm.ctpop.i32 (i32)
declare i64 @llvm.ctpop.i64 (i64)
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