2014-04-30 07:05:07 +00:00
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; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 %s -o - \
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; RUN: | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
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; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -code-model=large %s -o - \
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; RUN: | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s
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define arm_aapcs_vfpcc void @check_watermark() {
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entry:
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%buffer = alloca [4096 x i8], align 1
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ret void
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}
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; CHECK-DEFAULT-CODE-MODEL: check_watermark:
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; CHECK-DEFAULT-CODE-MODEL: movw r4, #1024
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; CHECK-DEFAULT-CODE-MODEL: bl __chkstk
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; CHECK-DEFAULT-CODE-MODEL: sub.w sp, sp, r4
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; CHECK-LARGE-CODE-MODEL: check_watermark:
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; CHECK-LARGE-CODE-MODEL: movw r12, :lower16:__chkstk
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; CHECK-LARGE-CODE-MODEL: movt r12, :upper16:__chkstk
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ARM: correct bundle generation for MOV32T relocations
Although the previous code would construct a bundle and add the correct elements
to it, it would not finalise the bundle. This resulted in the InternalRead
markers not being added to the MachineOperands nor, more importantly, the
externally visible defs to the bundle itself. So, although the bundle was not
exposing the def, the generated code would be correct because there was no
optimisations being performed. When optimisations were enabled, the post
register allocator would kick in, and the hazard recognizer would reorder
operations around the load which would define the value being operated upon.
Rather than manually constructing the bundle, simply construct and finalise the
bundle via the finaliseBundle call after both MIs have been emitted. This
improves the code generation with optimisations where IMAGE_REL_ARM_MOV32T
relocations are emitted.
The changes to the other tests are the result of the bundle generation
preventing the scheduler from hoisting the moves across the loads. The net
effect of the generated code is equivalent, but, is much more identical to what
is actually being lowered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209267 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 01:25:24 +00:00
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; CHECK-LARGE-CODE-MODEL: movw r4, #1024
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2014-04-30 07:05:07 +00:00
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; CHECK-LARGE-CODE-MODEL: blx r12
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; CHECK-LARGE-CODE-MODEL: sub.w sp, sp, r4
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