2009-09-09 00:09:15 +00:00
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; RUN: llc < %s -march=arm -mattr=+neon
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2009-08-03 20:08:18 +00:00
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; PR4657
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
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target triple = "armv7-apple-darwin9"
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define arm_apcscc <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind {
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entry:
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%v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
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%f_addr = alloca i32 ; <i32*> [#uses=2]
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%retval = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
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%0 = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store <4 x i32> %v, <4 x i32>* %v_addr
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store i32 %f, i32* %f_addr
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%1 = load <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1]
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%2 = load i32* %f_addr, align 4 ; <i32> [#uses=1]
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%3 = insertelement <4 x i32> undef, i32 %2, i32 0 ; <<4 x i32>> [#uses=1]
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%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>> [#uses=1]
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%5 = mul <4 x i32> %1, %4 ; <<4 x i32>> [#uses=1]
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store <4 x i32> %5, <4 x i32>* %0, align 16
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%6 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
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store <4 x i32> %6, <4 x i32>* %retval, align 16
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br label %return
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return: ; preds = %entry
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%retval1 = load <4 x i32>* %retval ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %retval1
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}
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