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llvm-6502/test/CodeGen/AArch64/fast-isel-sdiv.ll

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[FastISel][AArch64] Custom lower sdiv by power-of-2. Emit an optimized instruction sequence for sdiv by power-of-2 depending on the exact flag. This fixes rdar://problem/18224511. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217986 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-17 21:55:55 +00:00
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
Change the fast-isel-abort option from bool to int to enable "levels" Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 18:32:11 +00:00
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
[FastISel][AArch64] Custom lower sdiv by power-of-2. Emit an optimized instruction sequence for sdiv by power-of-2 depending on the exact flag. This fixes rdar://problem/18224511. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217986 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-17 21:55:55 +00:00
define i32 @sdiv_i32_exact(i32 %a) {
; CHECK-LABEL: sdiv_i32_exact
; CHECK: asr {{w[0-9]+}}, w0, #3
%1 = sdiv exact i32 %a, 8
ret i32 %1
}
define i32 @sdiv_i32_pos(i32 %a) {
; CHECK-LABEL: sdiv_i32_pos
; CHECK: add [[REG1:w[0-9]+]], w0, #7
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
; CHECK-NEXT: asr {{w[0-9]+}}, [[REG2]], #3
%1 = sdiv i32 %a, 8
ret i32 %1
}
define i32 @sdiv_i32_neg(i32 %a) {
; CHECK-LABEL: sdiv_i32_neg
; CHECK: add [[REG1:w[0-9]+]], w0, #7
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
; CHECK-NEXT: neg {{w[0-9]+}}, [[REG2]], asr #3
%1 = sdiv i32 %a, -8
ret i32 %1
}
define i64 @sdiv_i64_exact(i64 %a) {
; CHECK-LABEL: sdiv_i64_exact
; CHECK: asr {{x[0-9]+}}, x0, #4
%1 = sdiv exact i64 %a, 16
ret i64 %1
}
define i64 @sdiv_i64_pos(i64 %a) {
; CHECK-LABEL: sdiv_i64_pos
; CHECK: add [[REG1:x[0-9]+]], x0, #15
; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
; CHECK-NEXT: asr {{x[0-9]+}}, [[REG2]], #4
%1 = sdiv i64 %a, 16
ret i64 %1
}
define i64 @sdiv_i64_neg(i64 %a) {
; CHECK-LABEL: sdiv_i64_neg
; CHECK: add [[REG1:x[0-9]+]], x0, #15
; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
; CHECK-NEXT: neg {{x[0-9]+}}, [[REG2]], asr #4
%1 = sdiv i64 %a, -16
ret i64 %1
}
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