llvm-6502/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll

;
; Register constraint "r" shouldn't take long long unless
; The target is 64 bit.
;
;
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s


define i32 @main() nounwind {
entry:


; r with long long
;CHECK:	#APP
;CHECK:	addiu ${{[0-9]+}},${{[0-9]+}},3
;CHECK:	#NO_APP
  tail call i64 asm sideeffect "addiu $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
  ret i32 0
}
Add support for the 'I' inline asm constraint. Also add tests from the previous 2 patches. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8 2012-05-07 03:13:32 +00:00			`;`
			`; Register constraint "r" shouldn't take long long unless`
			`; The target is 64 bit.`
			`;`
			`;`
			`; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s \| FileCheck %s`


			`define i32 @main() nounwind {`
			`entry:`


			`; r with long long`
			`;CHECK: #APP`
[mips] Use addiu in inline assembly tests since addi is not available in all ISA's Summary: This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when -integrated-as is enabled by default and we correctly detect the host CPU. No functional change since these tests are testing the behaviour of the constraint used for the third operand rather than the mnemonic. Depends on D3842 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3843 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209421 91177308-0d34-0410-b5e6-96231b3b80d8 2014-05-22 11:46:58 +00:00			`;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3`
Add support for the 'I' inline asm constraint. Also add tests from the previous 2 patches. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8 2012-05-07 03:13:32 +00:00			`;CHECK: #NO_APP`
[mips] Use addiu in inline assembly tests since addi is not available in all ISA's Summary: This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when -integrated-as is enabled by default and we correctly detect the host CPU. No functional change since these tests are testing the behaviour of the constraint used for the third operand rather than the mnemonic. Depends on D3842 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3843 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209421 91177308-0d34-0410-b5e6-96231b3b80d8 2014-05-22 11:46:58 +00:00			`tail call i64 asm sideeffect "addiu $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind`
Add support for the 'I' inline asm constraint. Also add tests from the previous 2 patches. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8 2012-05-07 03:13:32 +00:00			`ret i32 0`
			`}`