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llvm-6502/test/CodeGen/X86/zext-fold.ll

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Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 23:33:07 +00:00
; RUN: llc < %s -mcpu=generic -march=x86 -enable-misched=false | FileCheck %s
Add a DAGCombine for (ext (binop (load x), cst)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 01:15:49 +00:00
;; Simple case
define i32 @test1(i8 %x) nounwind readnone {
%A = and i8 %x, -32
%B = zext i8 %A to i32
ret i32 %B
}
; CHECK: test1
; CHECK: movzbl
; CHECK-NEXT: andl {{.*}}224
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 23:33:07 +00:00
;; Multiple uses of %x but easily extensible.
Add a DAGCombine for (ext (binop (load x), cst)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 01:15:49 +00:00
define i32 @test2(i8 %x) nounwind readnone {
%A = and i8 %x, -32
%B = zext i8 %A to i32
%C = or i8 %x, 63
%D = zext i8 %C to i32
%E = add i32 %B, %D
ret i32 %E
}
; CHECK: test2
; CHECK: movzbl
Revert "Temporarily enable MI-Sched on X86." This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:48:58 +00:00
; CHECK: andl $224
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 23:33:07 +00:00
; CHECK: orl $63
Add a DAGCombine for (ext (binop (load x), cst)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 01:15:49 +00:00
declare void @use(i32, i8)
;; Multiple uses of %x where we shouldn't extend the load.
define void @test3(i8 %x) nounwind readnone {
%A = and i8 %x, -32
%B = zext i8 %A to i32
call void @use(i32 %B, i8 %x)
ret void
}
; CHECK: test3
llvm/test/CodeGen/X86/zext-fold.ll: Relax an expression in stack offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147928 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 07:34:22 +00:00
; CHECK: movzbl {{[0-9]+}}(%esp), [[REGISTER:%e[a-z]{2}]]
There's no need to be so picky about the particular register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 21:00:00 +00:00
; CHECK-NEXT: movl [[REGISTER]], 4(%esp)
; CHECK-NEXT: andl $224, [[REGISTER]]
; CHECK-NEXT: movl [[REGISTER]], (%esp)
Commit the right set of tests for r133124. Sorry 'bout that! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 01:35:45 +00:00
; CHECK-NEXT: call{{.*}}use
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