llvm-6502/test/CodeGen/ARM/ispositive.ll

; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s

define i32 @test1(i32 %X) {
; CHECK: lsr{{.*}}#31
entry:
        icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
        zext i1 %0 to i32               ; <i32>:1 [#uses=1]
        ret i32 %1
}
ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8 2014-04-03 16:01:44 +00:00			`; RUN: llc -mtriple=arm-eabi %s -o - \| FileCheck %s`
new testcase git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35882 91177308-0d34-0410-b5e6-96231b3b80d8 2007-04-11 05:32:13 +00:00
change test name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35904 91177308-0d34-0410-b5e6-96231b3b80d8 2007-04-11 15:24:04 +00:00			`define i32 @test1(i32 %X) {`
Update tests to handle MC-inst instruction printing of shift operations. The legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8 2010-09-17 21:58:46 +00:00			`; CHECK: lsr{{.*}}#31`
new testcase git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35882 91177308-0d34-0410-b5e6-96231b3b80d8 2007-04-11 05:32:13 +00:00			`entry:`
			`icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]`
			`zext i1 %0 to i32 ; <i32>:1 [#uses=1]`
			`ret i32 %1`
			`}`