llvm-6502/test/CodeGen/Mips/2008-07-06-fadd64.ll

; RUN: llvm-as < %s | llc -march=mips | grep __adddf3

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-psp-elf"

define double @dofloat(double %a, double %b) nounwind {
entry:
	fadd double %a, %b		; <double>:0 [#uses=1]
	ret double %0
}
Turn on LegalizeTypes, the new type legalization codegen infrastructure, by default. Please report any breakage to the mailing lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58232 91177308-0d34-0410-b5e6-96231b3b80d8 2008-10-27 08:42:46 +00:00			`; RUN: llvm-as < %s \| llc -march=mips \| grep __adddf3`
Batch 2 of Mips CodeGen tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54507 91177308-0d34-0410-b5e6-96231b3b80d8 2008-08-08 04:03:25 +00:00
			`target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"`
			`target triple = "mipsallegrexel-psp-elf"`

			`define double @dofloat(double %a, double %b) nounwind {`
			`entry:`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-04 22:49:04 +00:00			`fadd double %a, %b ; <double>:0 [#uses=1]`
Batch 2 of Mips CodeGen tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54507 91177308-0d34-0410-b5e6-96231b3b80d8 2008-08-08 04:03:25 +00:00			`ret double %0`
			`}`