mirror of
https://github.com/c64scene-ar/llvm-6502.git
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96 lines
2.0 KiB
LLVM
96 lines
2.0 KiB
LLVM
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; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
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define void @t0(i32 %a) nounwind {
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entry:
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; CHECK: t0
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; CHECK: str {{w[0-9]+}}, [sp, #12]
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; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
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; CHECK-NEXT: str [[REGISTER]], [sp, #12]
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; CHECK: ret
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr
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%tmp = load i32* %a.addr
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store i32 %tmp, i32* %a.addr
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ret void
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}
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define void @t1(i64 %a) nounwind {
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; CHECK: t1
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; CHECK: str {{x[0-9]+}}, [sp, #8]
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; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
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; CHECK-NEXT: str [[REGISTER]], [sp, #8]
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; CHECK: ret
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%a.addr = alloca i64, align 4
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store i64 %a, i64* %a.addr
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%tmp = load i64* %a.addr
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store i64 %tmp, i64* %a.addr
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ret void
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}
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define zeroext i1 @i1(i1 %a) nounwind {
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entry:
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; CHECK: @i1
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; CHECK: and w0, w0, #0x1
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; CHECK: strb w0, [sp, #15]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: and w0, w0, #0x1
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; CHECK: and w0, w0, #0x1
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; CHECK: add sp, sp, #16
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; CHECK: ret
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%a.addr = alloca i1, align 1
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store i1 %a, i1* %a.addr, align 1
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%0 = load i1* %a.addr, align 1
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ret i1 %0
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}
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define i32 @t2(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: ldur w0, [x0, #-4]
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; CHECK: ret
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%0 = getelementptr i32 *%ptr, i32 -1
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%1 = load i32* %0, align 4
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ret i32 %1
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}
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define i32 @t3(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: ldur w0, [x0, #-256]
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; CHECK: ret
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%0 = getelementptr i32 *%ptr, i32 -64
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%1 = load i32* %0, align 4
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ret i32 %1
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}
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define void @t4(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: movz w8, #0
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; CHECK: stur w8, [x0, #-4]
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; CHECK: ret
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%0 = getelementptr i32 *%ptr, i32 -1
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store i32 0, i32* %0, align 4
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ret void
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}
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define void @t5(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: movz w8, #0
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; CHECK: stur w8, [x0, #-256]
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; CHECK: ret
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%0 = getelementptr i32 *%ptr, i32 -64
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store i32 0, i32* %0, align 4
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ret void
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}
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define void @t6() nounwind {
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; CHECK: t6
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; CHECK: brk #1
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tail call void @llvm.trap()
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ret void
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}
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declare void @llvm.trap() nounwind
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