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llvm-6502/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll

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PR11868. The previous loop in LiveIntervals::join would sometimes fall over if more than two adjacent ranges needed to be merged. The new version should be able to handle an arbitrary sequence of adjancent ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 05:37:34 +00:00
; RUN: llc -verify-coalescing < %s
; PR11868
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi"
%0 = type { <4 x float> }
%1 = type { <4 x float> }
@foo = external global %0, align 16
define arm_aapcs_vfpcc void @bar(float, i1 zeroext, i1 zeroext) nounwind {
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00
%4 = load <4 x float>, <4 x float>* getelementptr inbounds (%0* @foo, i32 0, i32 0), align 16
PR11868. The previous loop in LiveIntervals::join would sometimes fall over if more than two adjacent ranges needed to be merged. The new version should be able to handle an arbitrary sequence of adjancent ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 05:37:34 +00:00
%5 = extractelement <4 x float> %4, i32 0
%6 = extractelement <4 x float> %4, i32 1
%7 = extractelement <4 x float> %4, i32 2
%8 = insertelement <4 x float> undef, float %5, i32 0
%9 = insertelement <4 x float> %8, float %6, i32 1
%10 = insertelement <4 x float> %9, float %7, i32 2
%11 = insertelement <4 x float> %10, float 0.000000e+00, i32 3
store <4 x float> %11, <4 x float>* undef, align 16
call arm_aapcs_vfpcc void @baz(%1* undef, float 0.000000e+00) nounwind
ret void
}
declare arm_aapcs_vfpcc void @baz(%1*, float)
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