llvm-6502/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt

# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s

# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
# -------------------------------------------------------------------------------------------------
#
# if t == 15 then UNPREDICTABLE

# CHECK: warning: potentially undefined instruction encoding
0x00 0xf0 0xcf 0xe7
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8 2012-03-20 15:54:56 +00:00			`# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 \|& FileCheck %s`
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-11 18:34:12 +00:00
			`# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7)`
Continue to tighten decoding by performing more operand validation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-11 20:21:46 +00:00			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-11 18:34:12 +00:00			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 1: 1: 0\| 0: 1: 1: 1\| 1: 1: 0: 0\| 1: 1: 1: 1\| 1: 1: 1: 1\| 0: 0: 0: 0\| 0: 0: 0: 0\| 0: 0: 0: 0\|`
			`# -------------------------------------------------------------------------------------------------`
Continue to tighten decoding by performing more operand validation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-11 20:21:46 +00:00			`#`
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-11 18:34:12 +00:00			`# if t == 15 then UNPREDICTABLE`
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8 2012-03-20 15:54:56 +00:00
			`# CHECK: warning: potentially undefined instruction encoding`
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-11 18:34:12 +00:00			`0x00 0xf0 0xcf 0xe7`