2009-09-08 23:54:48 +00:00
|
|
|
; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep CPI
|
- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47290 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-18 23:04:32 +00:00
|
|
|
|
|
|
|
|
define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
|
|
|
|
|
%tmp1 = bitcast <2 x i64> %b1 to <8 x i16>
|
|
|
|
|
%tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > to <8 x i16>) ) nounwind readnone
|
|
|
|
|
%tmp3 = bitcast <8 x i16> %tmp2 to <2 x i64>
|
|
|
|
|
ret <2 x i64> %tmp3
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @t2(<2 x i64> %b1, <2 x i64> %c) nounwind {
|
|
|
|
|
%tmp1 = bitcast <2 x i64> %b1 to <4 x i32>
|
|
|
|
|
%tmp2 = tail call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> %tmp1, <4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > ) nounwind readnone
|
|
|
|
|
ret <4 x i32> %tmp2
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
|
|
|
|
|
declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
|
