2013-03-25 23:37:17 +00:00
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//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Sandy Bridge to support instruction
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// scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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def SandyBridgeModel : SchedMachineModel {
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// All x86 instructions are modeled as a single micro-op, and SB can decode 4
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// instructions per cycle.
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// FIXME: Identify instructions that aren't a single fused micro-op.
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let IssueWidth = 4;
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let MinLatency = 0; // 0 = Out-of-order execution.
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let LoadLatency = 4;
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let MispredictPenalty = 16;
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}
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let SchedModel = SandyBridgeModel in {
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// Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
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// Ports 0, 1, and 5 handle all computation.
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def SBPort0 : ProcResource<1>;
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def SBPort1 : ProcResource<1>;
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def SBPort5 : ProcResource<1>;
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// Ports 2 and 3 are identical. They handle loads and the address half of
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// stores.
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def SBPort23 : ProcResource<2>;
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// Port 4 gets the data half of stores. Store data can be available later than
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// the store address, but since we don't model the latency of stores, we can
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// ignore that.
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def SBPort4 : ProcResource<1>;
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// Many micro-ops are capable of issuing on multiple ports.
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def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
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def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
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def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
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2013-04-02 01:58:47 +00:00
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// Integer division issued on port 0.
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def SBDivider : ProcResource<1>;
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2013-03-25 23:37:17 +00:00
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// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 4>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when queued in the reservation station.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
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ProcResourceKind ExePort,
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int Lat> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
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// Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
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let Latency = !add(Lat, 4);
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}
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}
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// A folded store needs a cycle on port 4 for the store data, but it does not
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// need an extra port 2/3 cycle to recompute the address.
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def : WriteRes<WriteRMW, [SBPort4]>;
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def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
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def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; }
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def : WriteRes<WriteMove, [SBPort015]>;
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def : WriteRes<WriteZero, []>;
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defm : SBWriteResPair<WriteALU, SBPort015, 1>;
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defm : SBWriteResPair<WriteIMul, SBPort1, 3>;
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defm : SBWriteResPair<WriteShift, SBPort05, 1>;
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defm : SBWriteResPair<WriteJump, SBPort5, 1>;
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// This is for simple LEAs with one or two input operands.
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// The complex ones can only execute on port 1, and they require two cycles on
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// the port to read all inputs. We don't model that.
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def : WriteRes<WriteLEA, [SBPort15]>;
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// This is quite rough, latency depends on the dividend.
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def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> {
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let Latency = 25;
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let ResourceCycles = [1, 10];
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}
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def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> {
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let Latency = 29;
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let ResourceCycles = [1, 1, 10];
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}
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// Scalar and vector floating point.
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defm : SBWriteResPair<WriteFAdd, SBPort1, 3>;
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defm : SBWriteResPair<WriteFMul, SBPort0, 5>;
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defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles.
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defm : SBWriteResPair<WriteFRcp, SBPort0, 5>;
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defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>;
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defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>;
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defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>;
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defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>;
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// Vector integer operations.
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defm : SBWriteResPair<WriteVecShift, SBPort05, 1>;
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defm : SBWriteResPair<WriteVecLogic, SBPort015, 1>;
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defm : SBWriteResPair<WriteVecALU, SBPort15, 1>;
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defm : SBWriteResPair<WriteVecIMul, SBPort0, 5>;
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defm : SBWriteResPair<WriteShuffle, SBPort15, 1>;
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def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
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def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
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} // SchedModel
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