llvm-6502/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt

# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s

# Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 0: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# DPFrm with bad reg specifier(s)
#
# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
0x9f 0x5f 0x66 0xe6

# CHECK: warning: potentially undefined
# CHECK: uqadd8	r5, r6, pc
Convert the uses of '\|&' to use '2>&1 \|' instead, which works on old versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159544 91177308-0d34-0410-b5e6-96231b3b80d8 2012-07-02 18:37:59 +00:00			`# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 \| FileCheck %s`
Add sanity checking for bad register specifier(s) for the DPFrm instructions. Add more test cases to exercise the logical branches related to the above change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-08 00:29:09 +00:00
			`# Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4)`
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-10 00:03:03 +00:00			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
Add sanity checking for bad register specifier(s) for the DPFrm instructions. Add more test cases to exercise the logical branches related to the above change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-08 00:29:09 +00:00			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 1: 1: 0\| 0: 1: 1: 0\| 0: 1: 1: 0\| 0: 1: 1: 0\| 0: 1: 0: 1\| 1: 1: 1: 1\| 1: 0: 0: 1\| 1: 1: 1: 1\|`
			`# -------------------------------------------------------------------------------------------------`
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-10 00:03:03 +00:00			`#`
Add sanity checking for bad register specifier(s) for the DPFrm instructions. Add more test cases to exercise the logical branches related to the above change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-08 00:29:09 +00:00			`# DPFrm with bad reg specifier(s)`
			`#`
			`# if d == 15 \|\| n == 15 \|\| m == 15 then UNPREDICTABLE;`
			`0x9f 0x5f 0x66 0xe6`
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8 2012-03-20 15:54:56 +00:00
			`# CHECK: warning: potentially undefined`
			`# CHECK: uqadd8 r5, r6, pc`